{"id":"https://openalex.org/W2112564358","doi":"https://doi.org/10.1109/tcad.2010.2049057","title":"On Reducing Scan Shift Activity at RTL","display_name":"On Reducing Scan Shift Activity at RTL","publication_year":2010,"publication_date":"2010-06-24","ids":{"openalex":"https://openalex.org/W2112564358","doi":"https://doi.org/10.1109/tcad.2010.2049057","mag":"2112564358"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2010.2049057","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2010.2049057","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028556229","display_name":"Elif Alpaslan","orcid":null},"institutions":[{"id":"https://openalex.org/I27804330","display_name":"Brown University","ror":"https://ror.org/05gq02987","country_code":"US","type":"education","lineage":["https://openalex.org/I27804330"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Elif Alpaslan","raw_affiliation_strings":["Brown University, Providence, RI, USA","Brown University Providence RI USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brown University, Providence, RI, USA","institution_ids":["https://openalex.org/I27804330"]},{"raw_affiliation_string":"Brown University Providence RI USA","institution_ids":["https://openalex.org/I27804330"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101775144","display_name":"Yu Huang","orcid":"https://orcid.org/0000-0003-2619-4686"},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]},{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["HU","US"],"is_corresponding":false,"raw_author_name":"Yu Huang","raw_affiliation_strings":["Mentor Graphics Corporation, Wilsonville, OR, USA","Mentor Graphics Corp. Wilsonville, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I4210156212"]},{"raw_affiliation_string":"Mentor Graphics Corp. Wilsonville, OR, USA","institution_ids":["https://openalex.org/I105695857"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103033725","display_name":"Xijiang Lin","orcid":"https://orcid.org/0000-0003-1794-3788"},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]},{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["HU","US"],"is_corresponding":false,"raw_author_name":"Xijiang Lin","raw_affiliation_strings":["Mentor Graphics Corporation, Wilsonville, OR, USA","Mentor Graphics Corp. Wilsonville, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I4210156212"]},{"raw_affiliation_string":"Mentor Graphics Corp. Wilsonville, OR, USA","institution_ids":["https://openalex.org/I105695857"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020407423","display_name":"Wu-Tung Cheng","orcid":"https://orcid.org/0000-0001-6327-2394"},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]},{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["HU","US"],"is_corresponding":false,"raw_author_name":"Wu-Tung Cheng","raw_affiliation_strings":["Mentor Graphics Corporation, Wilsonville, OR, USA","Mentor Graphics Corp. Wilsonville, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I4210156212"]},{"raw_affiliation_string":"Mentor Graphics Corp. Wilsonville, OR, USA","institution_ids":["https://openalex.org/I105695857"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044465911","display_name":"Jennifer Dworak","orcid":null},"institutions":[{"id":"https://openalex.org/I27804330","display_name":"Brown University","ror":"https://ror.org/05gq02987","country_code":"US","type":"education","lineage":["https://openalex.org/I27804330"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jennifer Dworak","raw_affiliation_strings":["Brown University, Providence, RI, USA","Brown University Providence RI USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brown University, Providence, RI, USA","institution_ids":["https://openalex.org/I27804330"]},{"raw_affiliation_string":"Brown University Providence RI USA","institution_ids":["https://openalex.org/I27804330"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.998,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.78103022,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"29","issue":"7","first_page":"1110","last_page":"1120"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6577323079109192},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6291366815567017},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5747222900390625},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.521450936794281},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5202739834785461},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5055656433105469},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.49199315905570984},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.4704788327217102},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.45848414301872253},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.45602697134017944},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.4455243647098541},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.4239296019077301},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4217264950275421},{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.41998499631881714},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4034651815891266},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3912939429283142},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2385534942150116},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21235385537147522},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15597063302993774}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6577323079109192},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6291366815567017},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5747222900390625},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.521450936794281},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5202739834785461},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5055656433105469},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.49199315905570984},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.4704788327217102},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.45848414301872253},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.45602697134017944},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.4455243647098541},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.4239296019077301},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4217264950275421},{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.41998499631881714},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4034651815891266},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3912939429283142},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2385534942150116},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21235385537147522},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15597063302993774},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2010.2049057","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2010.2049057","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":44,"referenced_works":["https://openalex.org/W1557977552","https://openalex.org/W1568407911","https://openalex.org/W1823875934","https://openalex.org/W1843801354","https://openalex.org/W1900996732","https://openalex.org/W1914799182","https://openalex.org/W1966348745","https://openalex.org/W2059328769","https://openalex.org/W2079150276","https://openalex.org/W2080510479","https://openalex.org/W2098142277","https://openalex.org/W2102168889","https://openalex.org/W2105750980","https://openalex.org/W2105897317","https://openalex.org/W2106303764","https://openalex.org/W2112129823","https://openalex.org/W2113809744","https://openalex.org/W2115852918","https://openalex.org/W2119691242","https://openalex.org/W2120960137","https://openalex.org/W2126152478","https://openalex.org/W2126641963","https://openalex.org/W2126872604","https://openalex.org/W2130439920","https://openalex.org/W2131779957","https://openalex.org/W2132733952","https://openalex.org/W2133640956","https://openalex.org/W2136567303","https://openalex.org/W2136680550","https://openalex.org/W2140753143","https://openalex.org/W2146893269","https://openalex.org/W2150448461","https://openalex.org/W2153229449","https://openalex.org/W2155936784","https://openalex.org/W2160621850","https://openalex.org/W2162248293","https://openalex.org/W2166163625","https://openalex.org/W2169734655","https://openalex.org/W2170506040","https://openalex.org/W2538602038","https://openalex.org/W6678830865","https://openalex.org/W6678897769","https://openalex.org/W6680497249","https://openalex.org/W6683240559"],"related_works":["https://openalex.org/W1974621628","https://openalex.org/W2752479413","https://openalex.org/W2118952760","https://openalex.org/W2120257283","https://openalex.org/W2117563988","https://openalex.org/W2161696808","https://openalex.org/W4240466429","https://openalex.org/W2105463797","https://openalex.org/W4233954302","https://openalex.org/W2154529098"],"abstract_inverted_index":{"Power":[0],"dissipation":[1],"in":[2,59,91],"digital":[3],"circuits":[4],"during":[5,14,80,99,116,130],"scan-based":[6],"test":[7,20,54],"is":[8,102,133],"generally":[9],"much":[10],"higher":[11],"than":[12,110],"that":[13,26,144,180],"functional":[15,120],"operation.":[16,84,121],"Unfortunately,":[17],"this":[18,67],"increased":[19],"power":[21,55,182],"can":[22,39,184],"create":[23],"hot":[24],"spots":[25],"may":[27,56,145],"damage":[28],"the":[29,31,36,47,86,92,111,117,141,152,156,159,166],"silicon,":[30],"bonding":[32],"wires,":[33],"and":[34,164,175],"even":[35],"package.":[37],"It":[38],"also":[40,57],"cause":[41],"intensive":[42],"erosion":[43],"of":[44,49,74,83,89,95,114,136],"conductors-severely":[45],"decreasing":[46],"reliability":[48],"a":[50,71,75,96],"device.":[51],"Finally,":[52],"excessive":[53],"result":[58],"extra":[60],"yield":[61],"loss.":[62],"To":[63],"address":[64],"these":[65],"issues,":[66],"paper":[68],"first":[69],"presents":[70],"detailed":[72],"investigation":[73],"benchmark":[76,97],"circuit's":[77,118],"switching":[78,128],"activity":[79,129],"different":[81],"modes":[82],"Specifically,":[85],"average":[87,112],"number":[88,113],"transitions":[90,115],"combinational":[93],"logic":[94,139],"circuit":[98,127],"scan":[100,131],"shift":[101,132],"found":[103],"to":[104,169],"be":[105,185],"approximately":[106],"2.5":[107],"times":[108],"more":[109],"normal":[119],"A":[122],"DFT-based":[123],"approach":[124],"for":[125],"reducing":[126],"proposed.":[134],"Instead":[135],"inserting":[137],"additional":[138,147],"at":[140,158],"gate":[142],"level":[143,162],"introduce":[146],"delay":[148],"on":[149],"critical":[150],"paths,":[151],"proposed":[153],"method":[154],"modifies":[155],"design":[157],"register":[160],"transfer":[161],"(RTL)":[163],"uses":[165],"synthesis":[167],"tools":[168],"automatically":[170],"deal":[171],"with":[172,187],"timing":[173],"analysis":[174],"optimization.":[176],"Our":[177],"experiments":[178],"show":[179],"significant":[181],"reduction":[183],"achieved":[186],"very":[188],"low":[189],"overhead.":[190]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}