{"id":"https://openalex.org/W2128920842","doi":"https://doi.org/10.1109/tcad.2010.2043588","title":"HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures","display_name":"HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures","publication_year":2010,"publication_date":"2010-04-26","ids":{"openalex":"https://openalex.org/W2128920842","doi":"https://doi.org/10.1109/tcad.2010.2043588","mag":"2128920842"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2010.2043588","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2010.2043588","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108744170","display_name":"Seungwhun Paik","orcid":null},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seungwhun Paik","raw_affiliation_strings":["Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea","[Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea]","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021863397","display_name":"Insup Shin","orcid":null},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Insup Shin","raw_affiliation_strings":["Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea","[Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea]","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049474875","display_name":"Taewhan Kim","orcid":"https://orcid.org/0000-0002-6114-3772"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Taewhan Kim","raw_affiliation_strings":["School of Electrical Engineering and Computer Science, Seoul National University, Seoul, South Korea","Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ. Seoul, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical Engineering and Computer Science, Seoul National University, Seoul, South Korea","institution_ids":["https://openalex.org/I139264467"]},{"raw_affiliation_string":"Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ. Seoul, South Korea","institution_ids":["https://openalex.org/I139264467"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020011072","display_name":"Youngsoo Shin","orcid":"https://orcid.org/0000-0002-7474-9212"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Youngsoo Shin","raw_affiliation_strings":["Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea","[Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea]","institution_ids":["https://openalex.org/I157485424"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.61,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.90488395,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"29","issue":"5","first_page":"657","last_page":"670"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.8341066837310791},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6907336711883545},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5083140730857849},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4628405272960663},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.4446582794189453},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.44186681509017944},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44102850556373596},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.342682808637619},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.3045494258403778},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13427019119262695},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.11971250176429749},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09809964895248413}],"concepts":[{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.8341066837310791},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6907336711883545},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5083140730857849},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4628405272960663},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.4446582794189453},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.44186681509017944},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44102850556373596},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.342682808637619},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3045494258403778},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13427019119262695},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.11971250176429749},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09809964895248413},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2010.2043588","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2010.2043588","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.800000011920929,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":49,"referenced_works":["https://openalex.org/W115461275","https://openalex.org/W1495418540","https://openalex.org/W1998200478","https://openalex.org/W2027077493","https://openalex.org/W2039232615","https://openalex.org/W2064559570","https://openalex.org/W2089192331","https://openalex.org/W2093332051","https://openalex.org/W2093842169","https://openalex.org/W2097774291","https://openalex.org/W2099516858","https://openalex.org/W2102504603","https://openalex.org/W2113059357","https://openalex.org/W2114266730","https://openalex.org/W2115468286","https://openalex.org/W2117378467","https://openalex.org/W2117917202","https://openalex.org/W2119299561","https://openalex.org/W2124438715","https://openalex.org/W2124808421","https://openalex.org/W2125117969","https://openalex.org/W2129183345","https://openalex.org/W2131065168","https://openalex.org/W2134354173","https://openalex.org/W2137116686","https://openalex.org/W2137686989","https://openalex.org/W2144109350","https://openalex.org/W2149778532","https://openalex.org/W2150541449","https://openalex.org/W2155911206","https://openalex.org/W2162109720","https://openalex.org/W2162238157","https://openalex.org/W2164209491","https://openalex.org/W2167036627","https://openalex.org/W2341350247","https://openalex.org/W3089937351","https://openalex.org/W4229693094","https://openalex.org/W4231455094","https://openalex.org/W4236892114","https://openalex.org/W4243213665","https://openalex.org/W4246946013","https://openalex.org/W4248172602","https://openalex.org/W4251497353","https://openalex.org/W4255969660","https://openalex.org/W6666544085","https://openalex.org/W6675391977","https://openalex.org/W6679918708","https://openalex.org/W6682881493","https://openalex.org/W6684096234"],"related_works":["https://openalex.org/W4245151507","https://openalex.org/W2612099726","https://openalex.org/W2111112953","https://openalex.org/W2172010869","https://openalex.org/W2160632767","https://openalex.org/W2145993717","https://openalex.org/W2122030400","https://openalex.org/W2352470693","https://openalex.org/W2073137766","https://openalex.org/W1924077319"],"abstract_inverted_index":{"Level-sensitive":[0],"latches":[1,46],"are":[2,12,89,93],"widely":[3],"used":[4,14],"in":[5,15,107,116,132,162],"high-performance":[6],"custom":[7],"designs":[8,160],"while":[9],"edge-triggered":[10],"flip-flops":[11],"predominantly":[13],"application-specific":[16],"integrated":[17,149],"circuits.":[18],"We":[19],"consider":[20],"a":[21,24,108,117,133,137,151,208],"latch":[22,67],"as":[23],"basis":[25],"for":[26],"storage":[27],"and":[28,39,70,91,145,189],"address":[29],"each":[30],"step":[31],"of":[32,45,114,143,196,207],"high-level":[33],"synthesis":[34,73],"(HLS),":[35],"including":[36],"scheduling,":[37,56],"allocation,":[38],"control":[40,72],"synthesis.":[41],"While":[42],"the":[43,52,55,57,71,80,96,104,112,121,128,141,171,179,205],"use":[44],"provides":[47],"an":[48,199],"opportunity":[49],"to":[50,61,75,78,86,110,135,170,177,198],"reduce":[51,111,178],"latency":[53,122,180],"during":[54],"register":[58,97,118],"allocation":[59,98],"has":[60,74],"take":[62],"extra":[63],"conflicts":[64],"caused":[65],"by":[66,102,126,181],"into":[68,150],"account,":[69],"be":[76,100,124],"tailored":[77],"support":[79],"latch-based":[81],"data-path.":[82],"Optimization":[83],"potentials":[84],"specific":[85],"this":[87],"HLS":[88,144],"identified":[90],"solutions":[92],"proposed.":[94],"Specifically,":[95],"can":[99,123],"improved":[101],"refining":[103],"operation":[105],"schedule":[106],"way":[109,134],"number":[113],"edges":[115],"conflict":[119],"graph;":[120],"reduced":[125],"adjusting":[127],"clock":[129],"duty":[130],"cycle":[131],"generate":[136],"tighter":[138],"schedule.":[139],"All":[140],"steps":[142],"optimization":[146],"procedures":[147],"were":[148],"framework":[152],"called":[153],"HLS-l.":[154],"It":[155],"was":[156,175],"tested":[157],"on":[158,183],"benchmark":[159],"implemented":[161],"1.1-V,":[163],"45":[164],"nm":[165],"complementary":[166],"metal-oxide-semiconductor":[167],"technology.":[168],"Compared":[169],"conventional":[172],"HLS,":[173],"HLS-l":[174,197],"able":[176],"18.2%":[182],"average":[184],"with":[185],"9.2%":[186],"less":[187,191],"area":[188],"16.0%":[190],"power":[192],"consumption.":[193],"The":[194],"application":[195],"industrial":[200],"example":[201],"is":[202],"demonstrated":[203],"through":[204],"design":[206],"module":[209],"extracted":[210],"from":[211],"H.264/advanced":[212],"video":[213],"coding.":[214]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
