{"id":"https://openalex.org/W2018645548","doi":"https://doi.org/10.1109/tcad.2010.2042900","title":"Macromodeling of the Memristor in SPICE","display_name":"Macromodeling of the Memristor in SPICE","publication_year":2010,"publication_date":"2010-03-24","ids":{"openalex":"https://openalex.org/W2018645548","doi":"https://doi.org/10.1109/tcad.2010.2042900","mag":"2018645548"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2010.2042900","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2010.2042900","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103122340","display_name":"\u00c1d\u00e1m R\u00e1k","orcid":"https://orcid.org/0000-0003-4363-9915"},"institutions":[{"id":"https://openalex.org/I31882830","display_name":"P\u00e1zm\u00e1ny P\u00e9ter Catholic University","ror":"https://ror.org/05v9kya57","country_code":"HU","type":"education","lineage":["https://openalex.org/I31882830"]}],"countries":["HU"],"is_corresponding":false,"raw_author_name":"\u00c1d\u00e1m Rak","raw_affiliation_strings":["Faculty of Information Technology, Pazmany Peter Catholic University, Budapest, Hungary","Fac. of Inf. Technol., Pazmany Peter Catholic Univ., Budapest, Hungary"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Information Technology, Pazmany Peter Catholic University, Budapest, Hungary","institution_ids":["https://openalex.org/I31882830"]},{"raw_affiliation_string":"Fac. of Inf. Technol., Pazmany Peter Catholic Univ., Budapest, Hungary","institution_ids":["https://openalex.org/I31882830"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071446072","display_name":"Gy\u00f6rgy Cserey","orcid":"https://orcid.org/0000-0002-6836-1502"},"institutions":[{"id":"https://openalex.org/I31882830","display_name":"P\u00e1zm\u00e1ny P\u00e9ter Catholic University","ror":"https://ror.org/05v9kya57","country_code":"HU","type":"education","lineage":["https://openalex.org/I31882830"]},{"id":"https://openalex.org/I7597260","display_name":"Hungarian Academy of Sciences","ror":"https://ror.org/02ks8qq67","country_code":"HU","type":"government","lineage":["https://openalex.org/I7597260"]}],"countries":["HU"],"is_corresponding":false,"raw_author_name":"Gy\u00f6rgy Cserey","raw_affiliation_strings":["Infobionic and Neurobiological Plasticity Research Group, Hungarian Academy of Sciences (ATOMKI), Budapest, Hungary","Infobionic & Neurobiological Plasticity Res. Group, Pazmany Peter Catholic Univ., Budapest, Hungary"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Infobionic and Neurobiological Plasticity Research Group, Hungarian Academy of Sciences (ATOMKI), Budapest, Hungary","institution_ids":["https://openalex.org/I7597260"]},{"raw_affiliation_string":"Infobionic & Neurobiological Plasticity Res. Group, Pazmany Peter Catholic Univ., Budapest, Hungary","institution_ids":["https://openalex.org/I31882830"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":22.3631,"has_fulltext":false,"cited_by_count":254,"citation_normalized_percentile":{"value":0.99642975,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":95,"max":100},"biblio":{"volume":"29","issue":"4","first_page":"632","last_page":"636"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.9400181174278259},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.8802769184112549},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6431951522827148},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5983518362045288},{"id":"https://openalex.org/keywords/memistor","display_name":"Memistor","score":0.585730254650116},{"id":"https://openalex.org/keywords/emphasis","display_name":"Emphasis (telecommunications)","score":0.47132185101509094},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4517495036125183},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4486366808414459},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38613981008529663},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3454691767692566},{"id":"https://openalex.org/keywords/control-engineering","display_name":"Control engineering","score":0.33998364210128784},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.31791186332702637},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24331289529800415},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.2364046573638916},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11394235491752625},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11353626847267151}],"concepts":[{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.9400181174278259},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.8802769184112549},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6431951522827148},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5983518362045288},{"id":"https://openalex.org/C1895703","wikidata":"https://www.wikidata.org/wiki/Q6034938","display_name":"Memistor","level":4,"score":0.585730254650116},{"id":"https://openalex.org/C177454536","wikidata":"https://www.wikidata.org/wiki/Q578290","display_name":"Emphasis (telecommunications)","level":2,"score":0.47132185101509094},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4517495036125183},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4486366808414459},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38613981008529663},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3454691767692566},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.33998364210128784},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.31791186332702637},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24331289529800415},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.2364046573638916},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11394235491752625},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11353626847267151},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2010.2042900","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2010.2042900","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.44999998807907104,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1507592446","https://openalex.org/W1520140750","https://openalex.org/W1922984659","https://openalex.org/W1976627866","https://openalex.org/W2018577927","https://openalex.org/W2045009304","https://openalex.org/W2112181056","https://openalex.org/W2162651880","https://openalex.org/W2261756486","https://openalex.org/W2603064927","https://openalex.org/W2781401138","https://openalex.org/W6736339276"],"related_works":["https://openalex.org/W3049246456","https://openalex.org/W4241208885","https://openalex.org/W2035017065","https://openalex.org/W2015297467","https://openalex.org/W4242780158","https://openalex.org/W2323645878","https://openalex.org/W2159731583","https://openalex.org/W2094066961","https://openalex.org/W2767118459","https://openalex.org/W1997629593"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"present":[4],"a":[5,24,56],"new":[6,34],"simulation":[7,39],"program":[8],"with":[9,36,80],"integrated":[10],"circuit":[11],"emphasis":[12],"macromodel":[13,21,77,88],"of":[14,49,61,70,75,86],"the":[15,45,50,59,66],"recently":[16],"physically":[17],"implemented":[18],"memristor.":[19],"This":[20],"could":[22],"be":[23],"powerful":[25],"tool":[26],"for":[27,58],"electrical":[28],"engineers":[29],"to":[30,44],"design":[31],"and":[32],"experiment":[33],"circuits":[35],"memristors.":[37],"Our":[38,53],"results":[40],"show":[41],"similar":[42],"behavior":[43],"already":[46],"published":[47,67],"measurements":[48],"physical":[51],"implementation.":[52],"approach":[54],"provides":[55],"solution":[57],"modeling":[60],"boundary":[62],"conditions":[63],"following":[64],"exactly":[65],"mathematical":[68],"model":[69],"HP":[71],"Labs.":[72],"The":[73,83],"functionality":[74],"our":[76,87],"is":[78,89],"demonstrated":[79],"computer":[81],"simulations.":[82],"source":[84],"code":[85],"provided.":[90]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":9},{"year":2021,"cited_by_count":13},{"year":2020,"cited_by_count":17},{"year":2019,"cited_by_count":18},{"year":2018,"cited_by_count":23},{"year":2017,"cited_by_count":15},{"year":2016,"cited_by_count":17},{"year":2015,"cited_by_count":23},{"year":2014,"cited_by_count":29},{"year":2013,"cited_by_count":30},{"year":2012,"cited_by_count":23}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}