{"id":"https://openalex.org/W2134487287","doi":"https://doi.org/10.1109/tcad.2009.2035580","title":"Layout Generator for Transistor-Level High-Density Regular Circuits","display_name":"Layout Generator for Transistor-Level High-Density Regular Circuits","publication_year":2010,"publication_date":"2010-01-26","ids":{"openalex":"https://openalex.org/W2134487287","doi":"https://doi.org/10.1109/tcad.2009.2035580","mag":"2134487287"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2009.2035580","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2009.2035580","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064821922","display_name":"Yi-Wei Lin","orcid":"https://orcid.org/0000-0001-8047-1977"},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yi-Wei Lin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA, USA","Dept. of Electr. & Comput. Eng., Univ. of California Santa Barbara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of California Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063371595","display_name":"Malgorzata Marek-Sadowska","orcid":"https://orcid.org/0000-0002-3934-7031"},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Marek-Sadowska","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA, USA","Dept. of Electr. & Comput. Eng., Univ. of California Santa Barbara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of California Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013238154","display_name":"W. Maly","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W.P. Maly","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, , USA","institution_ids":["https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.531,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.93099277,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"29","issue":"2","first_page":"197","last_page":"210"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.7270441651344299},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6843664050102234},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.6563122272491455},{"id":"https://openalex.org/keywords/footprint","display_name":"Footprint","score":0.653224766254425},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6369328498840332},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.6362733840942383},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6117530465126038},{"id":"https://openalex.org/keywords/limit","display_name":"Limit (mathematics)","score":0.5582745671272278},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5517180562019348},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.41392892599105835},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.40727102756500244},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.37879183888435364},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3511200547218323},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3468303084373474},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2115887701511383},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19414597749710083},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11253777146339417},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.09524345397949219},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.09235471487045288}],"concepts":[{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.7270441651344299},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6843664050102234},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.6563122272491455},{"id":"https://openalex.org/C132943942","wikidata":"https://www.wikidata.org/wiki/Q2562511","display_name":"Footprint","level":2,"score":0.653224766254425},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6369328498840332},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6362733840942383},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6117530465126038},{"id":"https://openalex.org/C151201525","wikidata":"https://www.wikidata.org/wiki/Q177239","display_name":"Limit (mathematics)","level":2,"score":0.5582745671272278},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5517180562019348},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.41392892599105835},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40727102756500244},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.37879183888435364},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3511200547218323},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3468303084373474},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2115887701511383},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19414597749710083},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11253777146339417},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.09524345397949219},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.09235471487045288},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2009.2035580","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2009.2035580","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1479863711","https://openalex.org/W1492192095","https://openalex.org/W1987067207","https://openalex.org/W1992712466","https://openalex.org/W2035368095","https://openalex.org/W2071589594","https://openalex.org/W2100344939","https://openalex.org/W2108795363","https://openalex.org/W2116625560","https://openalex.org/W2126446661","https://openalex.org/W2141803235","https://openalex.org/W3141776272","https://openalex.org/W3148190347","https://openalex.org/W6674862444"],"related_works":["https://openalex.org/W2330537534","https://openalex.org/W2368534554","https://openalex.org/W2148469257","https://openalex.org/W2999244305","https://openalex.org/W2168827721","https://openalex.org/W2094506573","https://openalex.org/W4249517016","https://openalex.org/W2730343163","https://openalex.org/W2031194604","https://openalex.org/W2134103321"],"abstract_inverted_index":{"<para":[0],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[1],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[2],"In":[3],"this":[4],"paper,":[5],"we":[6],"describe":[7],"an":[8,34],"automatic":[9],"place":[10],"and":[11,29,60,85],"route":[12],"strategy":[13],"for":[14],"a":[15,45],"high-density,":[16],"super-regular,":[17],"double-gate,":[18],"transistor-array-based":[19],"layout.":[20],"Interconnects":[21],"on":[22],"all":[23],"metal":[24],"layers":[25],"are":[26],"strictly":[27],"parallel":[28],"can":[30],"be":[31],"manufactured":[32],"by":[33],"optical":[35],"proximity":[36],"correction":[37],"free":[38],"process.":[39],"Our":[40,65],"objective":[41],"is":[42],"to":[43,50],"achieve":[44],"circuit":[46],"layout":[47,55],"area":[48],"equal":[49],"the":[51,79,82,86,90],"transistor":[52],"footprint.":[53],"Such":[54],"constraints":[56],"limit":[57],"routing":[58],"flexibility":[59],"render":[61],"traditional":[62],"approaches":[63],"impractical.":[64],"tools":[66],"automatically":[67],"generate":[68],"circuits":[69],"with":[70],"several":[71],"tens":[72],"of":[73,81,89],"transistors.":[74],"Experimental":[75],"results":[76],"demonstrate":[77],"both":[78],"efficiency":[80],"proposed":[83],"algorithms":[84],"high":[87],"quality":[88],"layouts":[91],"produced.":[92],"</para>":[93]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":4}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}