{"id":"https://openalex.org/W2113337109","doi":"https://doi.org/10.1109/tcad.2009.2013996","title":"Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty","display_name":"Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty","publication_year":2009,"publication_date":"2009-04-22","ids":{"openalex":"https://openalex.org/W2113337109","doi":"https://doi.org/10.1109/tcad.2009.2013996","mag":"2113337109"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2009.2013996","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2009.2013996","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101407572","display_name":"Yang Xu","orcid":"https://orcid.org/0000-0003-3068-8793"},"institutions":[{"id":"https://openalex.org/I180949307","display_name":"Illinois Institute of Technology","ror":"https://ror.org/037t3ry66","country_code":"US","type":"education","lineage":["https://openalex.org/I180949307"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Yang Xu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, IL, USA","Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, IL, USA","institution_ids":["https://openalex.org/I180949307"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL","institution_ids":["https://openalex.org/I180949307"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067913660","display_name":"Kan-Lin Hsiung","orcid":null},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kan-Lin Hsiung","raw_affiliation_strings":["Department of Electrical Engineering, Stanford University, Stanford, CA, USA","Dept. of Electr. Eng., Stanford Univ., Stanford, CA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Stanford University, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Stanford Univ., Stanford, CA#TAB#","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100353869","display_name":"Xin Li","orcid":"https://orcid.org/0000-0002-4510-2436"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xin Li","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004024474","display_name":"Lawrence T. Pileggi","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"L.T. Pileggi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011176205","display_name":"Stephen Boyd","orcid":"https://orcid.org/0000-0001-8353-6000"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.P. Boyd","raw_affiliation_strings":["Department of Electrical Engineering, Stanford University, Stanford, CA, USA","Dept. of Electr. Eng., Stanford Univ., Stanford, CA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Stanford University, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Stanford Univ., Stanford, CA#TAB#","institution_ids":["https://openalex.org/I97018004"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5101407572"],"corresponding_institution_ids":["https://openalex.org/I180949307"],"apc_list":null,"apc_paid":null,"fwci":2.7444,"has_fulltext":false,"cited_by_count":38,"citation_normalized_percentile":{"value":0.90521207,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"28","issue":"5","first_page":"623","last_page":"637"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10848","display_name":"Advanced Multi-Objective Optimization Algorithms","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11798","display_name":"Optimal Experimental Design Methods","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1803","display_name":"Management Science and Operations Research"},"field":{"id":"https://openalex.org/fields/18","display_name":"Decision Sciences"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.52132648229599},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5032300353050232},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.4917638599872589},{"id":"https://openalex.org/keywords/design-for-manufacturability","display_name":"Design for manufacturability","score":0.47463545203208923},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.47120732069015503},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4583425521850586},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.4390369653701782},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4288427233695984},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.41422390937805176},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.39274662733078003},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3600272536277771},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2703920006752014},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19913607835769653}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.52132648229599},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5032300353050232},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.4917638599872589},{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.47463545203208923},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.47120732069015503},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4583425521850586},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.4390369653701782},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4288427233695984},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.41422390937805176},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.39274662733078003},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3600272536277771},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2703920006752014},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19913607835769653},{"id":"https://openalex.org/C548081761","wikidata":"https://www.wikidata.org/wiki/Q180388","display_name":"Waste management","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tcad.2009.2013996","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2009.2013996","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.157.1341","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.157.1341","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.cmu.edu/~xinli/papers/2009_TCAD_oracle.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.398.8531","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.398.8531","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://stanford.edu/~boyd/papers/pdf/reg_analog_recourse_unc.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.47999998927116394,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320332500","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":53,"referenced_works":["https://openalex.org/W147475332","https://openalex.org/W1525409241","https://openalex.org/W1985691370","https://openalex.org/W1995285162","https://openalex.org/W1999357165","https://openalex.org/W2070334657","https://openalex.org/W2076875478","https://openalex.org/W2084575717","https://openalex.org/W2089105401","https://openalex.org/W2096205176","https://openalex.org/W2097941400","https://openalex.org/W2098675632","https://openalex.org/W2105497327","https://openalex.org/W2106476087","https://openalex.org/W2107825592","https://openalex.org/W2112915111","https://openalex.org/W2118158907","https://openalex.org/W2118565267","https://openalex.org/W2123309836","https://openalex.org/W2124700654","https://openalex.org/W2127451853","https://openalex.org/W2129898575","https://openalex.org/W2131909792","https://openalex.org/W2133599987","https://openalex.org/W2134849712","https://openalex.org/W2137037970","https://openalex.org/W2138908842","https://openalex.org/W2141001531","https://openalex.org/W2144546776","https://openalex.org/W2146444777","https://openalex.org/W2153797910","https://openalex.org/W2156362969","https://openalex.org/W2157754281","https://openalex.org/W2159012745","https://openalex.org/W2160235668","https://openalex.org/W2160564549","https://openalex.org/W2161359911","https://openalex.org/W2162964517","https://openalex.org/W2163565880","https://openalex.org/W2171048418","https://openalex.org/W2296319761","https://openalex.org/W2587605040","https://openalex.org/W3104786355","https://openalex.org/W3106992008","https://openalex.org/W4232193470","https://openalex.org/W4235520416","https://openalex.org/W4243003428","https://openalex.org/W4245806610","https://openalex.org/W4247282788","https://openalex.org/W4250589301","https://openalex.org/W4252378425","https://openalex.org/W4300260142","https://openalex.org/W6631407737"],"related_works":["https://openalex.org/W2070693700","https://openalex.org/W3200538824","https://openalex.org/W1561071093","https://openalex.org/W2388589331","https://openalex.org/W4246351405","https://openalex.org/W2017322750","https://openalex.org/W4295186528","https://openalex.org/W2549099758","https://openalex.org/W624406738","https://openalex.org/W1573321145"],"abstract_inverted_index":{"Long":[0],"design":[1,34,58,87,145,210],"cycles":[2],"due":[3],"to":[4,7,42,47,142,214],"the":[5,30,44,62,109,130,144,151,168,204],"inability":[6],"predict":[8],"silicon":[9],"realities":[10],"are":[11,171,212],"a":[12,80,101,119,174,190],"well-known":[13],"problem":[14,24,111],"that":[15],"plagues":[16],"analog/RF":[17,57,76,82],"integrated":[18],"circuit":[19],"product":[20],"development.":[21],"As":[22],"this":[23],"worsens":[25],"for":[26,74,128,158,180],"nanoscale":[27,75],"IC":[28,83],"technologies,":[29],"high":[31],"cost":[32],"of":[33,68,92,103,161,167,192],"and":[35,53,66,105,134,198],"multiple":[36],"manufacturing":[37],"spins":[38],"causes":[39],"fewer":[40],"products":[41],"have":[43],"volume":[45],"required":[46],"support":[48],"full-custom":[49],"implementation.":[50],"Design":[51],"reuse":[52,104],"analog":[54],"synthesis":[55,110],"make":[56],"more":[59],"affordable;":[60],"however,":[61],"increasing":[63],"process":[64,169],"variability":[65,147],"lack":[67],"modeling":[69],"accuracy":[70],"remain":[71],"extremely":[72],"challenging":[73],"design.":[77],"We":[78,177],"propose":[79],"regular":[81,162,181],"using":[84,186,203],"metal-mask":[85,187,205],"configurability":[86],"methodology":[88,153],"Optimization":[89],"with":[90,115,123,146,218],"Recourse":[91],"Analog":[93],"Circuits":[94],"including":[95],"Layout":[96],"Extraction":[97],"(ORACLE),":[98],"which":[99],"is":[100,140,201],"combination":[102],"shared-use":[106],"by":[107,154,173],"formulating":[108],"as":[112],"an":[113],"optimization":[114,139],"recourse":[116,124],"problem.":[117],"Using":[118],"two-stage":[120],"geometric":[121],"programming":[122],"approach,":[125],"ORACLE":[126,152,179],"solves":[127],"both":[129],"globally":[131],"optimal":[132],"shared":[133],"application-specific":[135,199],"variables.":[136],"Furthermore,":[137],"robust":[138,216],"proposed":[141],"treat":[143],"problem,":[148],"further":[149],"enhancing":[150],"providing":[155],"yield":[156,220],"bound":[157],"each":[159],"configuration":[160],"designs.":[163],"The":[164],"statistical":[165],"variations":[166],"parameters":[170],"captured":[172],"confidence":[175],"ellipsoid.":[176],"demonstrate":[178],"Low":[182],"Noise":[183],"Amplifier":[184],"designs":[185,217],"configurability,":[188],"where":[189],"range":[191],"applications":[193],"share":[194],"common":[195],"underlying":[196],"structure":[197],"customization":[200],"performed":[202],"layers.":[206],"Two":[207],"RF":[208],"oscillator":[209],"examples":[211],"shown":[213],"achieve":[215],"guaranteed":[219],"bound.":[221]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-28T14:05:53.105641","created_date":"2025-10-10T00:00:00"}
