{"id":"https://openalex.org/W2180499911","doi":"https://doi.org/10.1109/tcad.2008.2006155","title":"RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm","display_name":"RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm","publication_year":2008,"publication_date":"2008-11-25","ids":{"openalex":"https://openalex.org/W2180499911","doi":"https://doi.org/10.1109/tcad.2008.2006155","mag":"2180499911"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2008.2006155","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2008.2006155","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067863557","display_name":"David Papa","orcid":null},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"David A. Papa","raw_affiliation_strings":["Electr. Eng. & Comput. Sci. Dept., Michigan Univ., Ann Arbor, MI","Electrical Engineering and Computer Science Department, University of Michigan, Ann Arbor, USA"],"affiliations":[{"raw_affiliation_string":"Electr. Eng. & Comput. Sci. Dept., Michigan Univ., Ann Arbor, MI","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"Electrical Engineering and Computer Science Department, University of Michigan, Ann Arbor, USA","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002713029","display_name":"Tao Luo","orcid":"https://orcid.org/0000-0003-4870-5942"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tao Luo","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas, Austin, Austin, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas, Austin, Austin, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103236778","display_name":"Michael D. Moffitt","orcid":"https://orcid.org/0000-0002-7655-5024"},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael D. Moffitt","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, USA"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, USA","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111946180","display_name":"C. N. Sze","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C. N. Sze","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, USA"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, USA","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100448036","display_name":"Zhuo Li","orcid":"https://orcid.org/0000-0002-9937-2669"},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhuo Li","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, USA"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, USA","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043138186","display_name":"Gi-Joon Nam","orcid":"https://orcid.org/0000-0001-6355-2935"},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gi-Joon Nam","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, USA"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, USA","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113656006","display_name":"Charles J. Alpert","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Charles J. Alpert","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, USA"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, USA","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065370018","display_name":"Igor L. Markov","orcid":"https://orcid.org/0000-0002-3826-527X"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Igor L. Markov","raw_affiliation_strings":["Electr. Eng. & Comput. Sci. Dept., Michigan Univ., Ann Arbor, MI","Electrical Engineering and Computer Science Department, University of Michigan, Ann Arbor, USA"],"affiliations":[{"raw_affiliation_string":"Electr. Eng. & Comput. Sci. Dept., Michigan Univ., Ann Arbor, MI","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"Electrical Engineering and Computer Science Department, University of Michigan, Ann Arbor, USA","institution_ids":["https://openalex.org/I27837315"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5067863557"],"corresponding_institution_ids":["https://openalex.org/I27837315"],"apc_list":null,"apc_paid":null,"fwci":3.051,"has_fulltext":false,"cited_by_count":26,"citation_normalized_percentile":{"value":0.91643114,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"27","issue":"12","first_page":"2156","last_page":"2168"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/rumble","display_name":"Rumble","score":0.7996593117713928},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.6708153486251831},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6702987551689148},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5559261441230774},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5381447076797485},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.5125694274902344},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.49891209602355957},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.486743688583374},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.47786539793014526},{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.43925753235816956},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4214032292366028},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.36110642552375793},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3375779390335083},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33349114656448364},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.19749310612678528},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.18720781803131104},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.14759108424186707}],"concepts":[{"id":"https://openalex.org/C2779390954","wikidata":"https://www.wikidata.org/wiki/Q17084008","display_name":"Rumble","level":2,"score":0.7996593117713928},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.6708153486251831},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6702987551689148},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5559261441230774},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5381447076797485},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.5125694274902344},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.49891209602355957},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.486743688583374},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.47786539793014526},{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.43925753235816956},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4214032292366028},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.36110642552375793},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3375779390335083},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33349114656448364},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.19749310612678528},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.18720781803131104},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.14759108424186707},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tcad.2008.2006155","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2008.2006155","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.129.8804","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.129.8804","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecs.umich.edu/~mmoffitt/papers/papa_ispd2008.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.217.5555","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.217.5555","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecs.umich.edu/~imarkov/pubs/jour/tcad09-rumble.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1978865105","https://openalex.org/W1999938868","https://openalex.org/W2000089152","https://openalex.org/W2003764518","https://openalex.org/W2012173826","https://openalex.org/W2025892554","https://openalex.org/W2076265641","https://openalex.org/W2093380260","https://openalex.org/W2097845952","https://openalex.org/W2098463580","https://openalex.org/W2102182481","https://openalex.org/W2107966189","https://openalex.org/W2108411416","https://openalex.org/W2113202945","https://openalex.org/W2115819745","https://openalex.org/W2121244114","https://openalex.org/W2124481761","https://openalex.org/W2137589342","https://openalex.org/W2139071021","https://openalex.org/W2165120956","https://openalex.org/W2166378964","https://openalex.org/W2169049905","https://openalex.org/W3147222035","https://openalex.org/W4237144696","https://openalex.org/W4237770439","https://openalex.org/W4238070904","https://openalex.org/W6678234960"],"related_works":["https://openalex.org/W2132668926","https://openalex.org/W2160596219","https://openalex.org/W4232821362","https://openalex.org/W2163932442","https://openalex.org/W2735446578","https://openalex.org/W2376650996","https://openalex.org/W2543290882","https://openalex.org/W2148414872","https://openalex.org/W1736185682","https://openalex.org/W2030683669"],"abstract_inverted_index":{"Physical-synthesis":[0],"tools":[1],"are":[2,14],"responsible":[3],"for":[4,32,73,106],"achieving":[5],"timing":[6,49,53,67,72],"closure.":[7],"Starting":[8],"with":[9,41,65],"130-nm":[10],"designs,":[11],"multiple":[12,57],"cycles":[13],"required":[15],"to":[16,24,51,69],"cross":[17],"the":[18,71,90,93],"chip,":[19],"making":[20],"latch":[21,33],"placement":[22,34],"critical":[23,74],"success.":[25],"We":[26],"present":[27],"a":[28,47,107],"new":[29],"physical-synthesis":[30],"optimization":[31],"called":[35],"Rip":[36],"Up":[37],"and":[38,62,85],"Move":[39],"Boxes":[40],"Linear":[42],"Evaluation":[43],"(RUMBLE)":[44],"that":[45,76],"uses":[46],"linear":[48],"model":[50],"optimize":[52],"by":[54,81,99],"simultaneously":[55],"replacing":[56],"gates.":[58],"RUMBLE":[59],"runs":[60],"incrementally":[61],"in":[63],"conjunction":[64],"static":[66],"analysis":[68],"improve":[70,97],"paths":[75],"have":[77],"already":[78],"been":[79],"optimized":[80],"placement,":[82],"gate":[83],"sizing,":[84],"buffering.":[86],"Experimental":[87],"results":[88],"validate":[89],"effectiveness":[91],"of":[92,101],"approach:":[94],"Our":[95],"techniques":[96],"slack":[98],"41.3%":[100],"cycle":[102],"time":[103],"on":[104],"average":[105],"large":[108],"commercial":[109],"ASIC":[110],"design.":[111]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
