{"id":"https://openalex.org/W2121465016","doi":"https://doi.org/10.1109/tcad.2008.2006149","title":"Buffering Interconnect for Multicore Processor Designs","display_name":"Buffering Interconnect for Multicore Processor Designs","publication_year":2008,"publication_date":"2008-11-25","ids":{"openalex":"https://openalex.org/W2121465016","doi":"https://doi.org/10.1109/tcad.2008.2006149","mag":"2121465016"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2008.2006149","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2008.2006149","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049048133","display_name":"Yifang Liu","orcid":"https://orcid.org/0000-0003-3800-5512"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yifang Liu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Texas A and M University, College Station, TX, USA","Dept. of Electr. & Comput. Eng, Texas A&M Univ., College Station, TX#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Texas A and M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Texas A&M Univ., College Station, TX#TAB#","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103246390","display_name":"Jiang Hu","orcid":"https://orcid.org/0000-0003-1157-7799"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiang Hu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Texas A and M University, College Station, TX, USA","Dept. of Electr. & Comput. Eng, Texas A&M Univ., College Station, TX#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Texas A and M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Texas A&M Univ., College Station, TX#TAB#","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078773079","display_name":"Weiping Shi","orcid":"https://orcid.org/0000-0001-9773-9255"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Weiping Shi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Texas A and M University, College Station, TX, USA","Dept. of Electr. & Comput. Eng, Texas A&M Univ., College Station, TX#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Texas A and M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Texas A&M Univ., College Station, TX#TAB#","institution_ids":["https://openalex.org/I91045830"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I91045830"],"apc_list":null,"apc_paid":null,"fwci":0.6718,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.73893626,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"27","issue":"12","first_page":"2183","last_page":"2196"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7627854347229004},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.750566840171814},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7010045051574707},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6971415281295776},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5777682662010193},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5602098703384399},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.544459879398346},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40540459752082825},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.272523432970047},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08439886569976807}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7627854347229004},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.750566840171814},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7010045051574707},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6971415281295776},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5777682662010193},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5602098703384399},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.544459879398346},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40540459752082825},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.272523432970047},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08439886569976807},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2008.2006149","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2008.2006149","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5299999713897705}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1976809982","https://openalex.org/W2069162780","https://openalex.org/W2096341842","https://openalex.org/W2104116032","https://openalex.org/W2111320205","https://openalex.org/W2123316553","https://openalex.org/W2145091135","https://openalex.org/W2160252016","https://openalex.org/W2165120956","https://openalex.org/W4249030878","https://openalex.org/W4252747102","https://openalex.org/W4253824801","https://openalex.org/W6676815792"],"related_works":["https://openalex.org/W1542410906","https://openalex.org/W1970479385","https://openalex.org/W197049984","https://openalex.org/W1993191611","https://openalex.org/W2023938924","https://openalex.org/W2918840249","https://openalex.org/W1991859582","https://openalex.org/W2104702637","https://openalex.org/W2110053126","https://openalex.org/W2316512426"],"abstract_inverted_index":{"Recently,":[0],"the":[1,7,16,32,43,105,139,164,174],"microprocessor":[2],"industry":[3],"is":[4,25,70,91,180],"headed":[5],"in":[6,12,31,48,169],"direction":[8],"of":[9,34,85,138,177],"multicore":[10,37],"designs":[11],"order":[13],"to":[14,55,83,92,103],"continue":[15],"chip":[17],"performance":[18],"growth.":[19],"We":[20,121],"investigate":[21],"buffer":[22,46,68,130,141],"insertion,":[23,142],"which":[24],"a":[26,52,79,95,108,116,135],"critical":[27],"timing":[28,161,171],"optimization":[29],"technique,":[30],"context":[33],"an":[35],"industrial":[36],"processor":[38],"design":[39],"methodology.":[40],"Different":[41],"from":[42,97],"conventional":[44,67,140,166],"formulation,":[45],"insertion":[47,69,131],"this":[49],"case":[50],"requires":[51],"single":[53],"solution":[54,81,96,110],"accommodate":[56],"different":[57,80],"scenarios,":[58],"since":[59],"each":[60,73,84],"core":[61],"has":[62],"its":[63],"own":[64],"parameters.":[65],"If":[66],"performed":[71],"for":[72,111,119,126,151],"scenario":[74,99,113],"separately,":[75],"there":[76],"may":[77,114],"be":[78,115],"corresponding":[82],"these":[86,128],"scenarios.":[87,106],"A":[88],"straightforward":[89,136],"approach":[90],"judiciously":[93],"select":[94],"one":[98,112,118],"and":[100],"apply":[101],"it":[102],"all":[104],"However,":[107],"good":[109],"poor":[117],"another.":[120],"propose":[122],"several":[123],"algorithmic":[124],"techniques":[125],"solving":[127],"multiscenario":[129],"problems.":[132],"Compared":[133],"with":[134],"extension":[137],"our":[143,157,178],"algorithm":[144,158,179],"can":[145],"improve":[146],"slack":[147],"by":[148],"20-280":[149],"ps":[150],"max-slack":[152],"solutions.":[153],"For":[154],"min-cost":[155],"solutions,":[156],"causes":[159],"no":[160],"violation,":[162],"while":[163],"extended":[165],"buffering":[167],"results":[168],"35%":[170],"violations.":[172],"Moreover,":[173],"computation":[175],"speed":[176],"faster.":[181]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}