{"id":"https://openalex.org/W2165545669","doi":"https://doi.org/10.1109/tcad.2002.1013891","title":"Pattern routing: use and theory for increasing predictability and avoiding coupling","display_name":"Pattern routing: use and theory for increasing predictability and avoiding coupling","publication_year":2002,"publication_date":"2002-07-01","ids":{"openalex":"https://openalex.org/W2165545669","doi":"https://doi.org/10.1109/tcad.2002.1013891","mag":"2165545669"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2002.1013891","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2002.1013891","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000231774","display_name":"Ryan Kastner","orcid":"https://orcid.org/0000-0001-9062-5570"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Kastner","raw_affiliation_strings":["Computer Science Department, University of California, Los Angeles, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science Department, University of California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112310615","display_name":"Eli Bozorgzadeh","orcid":null},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"E. Bozorgzadeh","raw_affiliation_strings":["Computer Science Department, University of California, Los Angeles, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science Department, University of California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078132977","display_name":"Majid Sarrafzadeh","orcid":"https://orcid.org/0000-0001-8407-8689"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Sarrafzadeh","raw_affiliation_strings":["Computer Science Department, University of California, Los Angeles, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science Department, University of California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I161318765"],"apc_list":null,"apc_paid":null,"fwci":4.1202,"has_fulltext":false,"cited_by_count":146,"citation_normalized_percentile":{"value":0.94641958,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"21","issue":"7","first_page":"777","last_page":"790"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7602965831756592},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7576548457145691},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.5500206351280212},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.5396807789802551},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5390540361404419},{"id":"https://openalex.org/keywords/coupling","display_name":"Coupling (piping)","score":0.5014157295227051},{"id":"https://openalex.org/keywords/elmore-delay","display_name":"Elmore delay","score":0.48364579677581787},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.4779636561870575},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4110044538974762},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3503124415874481},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.29647940397262573},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.28985023498535156},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2534271478652954},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2427728772163391},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2080136239528656},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.17072796821594238}],"concepts":[{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7602965831756592},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7576548457145691},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.5500206351280212},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.5396807789802551},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5390540361404419},{"id":"https://openalex.org/C131584629","wikidata":"https://www.wikidata.org/wiki/Q4308705","display_name":"Coupling (piping)","level":2,"score":0.5014157295227051},{"id":"https://openalex.org/C84434228","wikidata":"https://www.wikidata.org/wiki/Q4531332","display_name":"Elmore delay","level":4,"score":0.48364579677581787},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.4779636561870575},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4110044538974762},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3503124415874481},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.29647940397262573},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.28985023498535156},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2534271478652954},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2427728772163391},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2080136239528656},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.17072796821594238},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1109/tcad.2002.1013891","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2002.1013891","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.14.9635","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.14.9635","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.ucsb.edu/~kastner/papers/tcad-pattern.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.16.3","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.16.3","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.ucla.edu/~elib/publications/journal/tcad-pattern_routing_use_theory.ps","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.28.6575","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.28.6575","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://beijing.cs.ucla.edu/~kastner/papers/tcad-PRELIM-pattern_routing_use_theory.ps","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.74.9857","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.74.9857","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ics.uci.edu/~eli/publications/journal/tcad-pattern_routing_use_theory.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320309652","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":55,"referenced_works":["https://openalex.org/W224253275","https://openalex.org/W1556480701","https://openalex.org/W1568614804","https://openalex.org/W1592614759","https://openalex.org/W1966624478","https://openalex.org/W1987786682","https://openalex.org/W1998626486","https://openalex.org/W2003160050","https://openalex.org/W2011039300","https://openalex.org/W2017416618","https://openalex.org/W2020905312","https://openalex.org/W2032145219","https://openalex.org/W2034118360","https://openalex.org/W2066356146","https://openalex.org/W2072230383","https://openalex.org/W2074799901","https://openalex.org/W2076265641","https://openalex.org/W2077950479","https://openalex.org/W2083554492","https://openalex.org/W2097371076","https://openalex.org/W2098047532","https://openalex.org/W2099862433","https://openalex.org/W2110759479","https://openalex.org/W2118211122","https://openalex.org/W2119215194","https://openalex.org/W2121424172","https://openalex.org/W2128106741","https://openalex.org/W2129570879","https://openalex.org/W2133994013","https://openalex.org/W2141778003","https://openalex.org/W2146414359","https://openalex.org/W2153580689","https://openalex.org/W2158598102","https://openalex.org/W2160252016","https://openalex.org/W2161182859","https://openalex.org/W2164456300","https://openalex.org/W2165437459","https://openalex.org/W2170086061","https://openalex.org/W2170949280","https://openalex.org/W2171347752","https://openalex.org/W2171938271","https://openalex.org/W2176610036","https://openalex.org/W2226297337","https://openalex.org/W2295318563","https://openalex.org/W2401610261","https://openalex.org/W4231541540","https://openalex.org/W4232051860","https://openalex.org/W4239470332","https://openalex.org/W4248699322","https://openalex.org/W4250174872","https://openalex.org/W4254557149","https://openalex.org/W4300809515","https://openalex.org/W6654707124","https://openalex.org/W6678077610","https://openalex.org/W6689238188"],"related_works":["https://openalex.org/W1995821058","https://openalex.org/W4321510758","https://openalex.org/W2163932442","https://openalex.org/W162881505","https://openalex.org/W2185927297","https://openalex.org/W3006432396","https://openalex.org/W2102676394","https://openalex.org/W2967850598","https://openalex.org/W2251104045","https://openalex.org/W2129468521"],"abstract_inverted_index":{"Deep":[0],"submicron":[1],"effects,":[2],"along":[3],"with":[4,89],"increasing":[5],"interconnect":[6,47,50,91,134],"densities,":[7],"have":[8],"increased":[9,37],"the":[10,13,70,76,117,127,144,147,168,171,192,202],"complexity":[11],"of":[12,30,39,66,72,119,146,170,181],"routing":[14,104,121,162,222],"problem.":[15],"Whereas":[16],"previously":[17],"we":[18,24,44,115,189,226],"could":[19],"focus":[20],"on":[21,201,229],"minimizing":[22,90],"wirelength,":[23],"must":[25,45],"now":[26],"consider":[27],"a":[28,63,82,130,179,207],"variety":[29],"objectives":[31],"during":[32],"routing.":[33,214,244],"For":[34],"example,":[35],"an":[36,102],"amount":[38],"timing":[40],"restrictions":[41],"means":[42],"that":[43,125,132,160,191],"minimize":[46],"delay.":[48],"But,":[49],"delay":[51,67,92,95,135],"is":[52,80,151,194],"no":[53],"longer":[54],"simply":[55],"related":[56],"to":[57,69,122,129,177,183,231],"wirelength.":[58],"Coupling":[59],"capacitance":[60],"has":[61],"become":[62],"dominant":[64],"component":[65],"due":[68],"shrinking":[71],"device":[73],"sizes.":[74],"Regardless,":[75],"most":[77],"important":[78],"objective":[79],"producing":[81],"routable":[83],"circuit.":[84,148,172],"Unfortunately,":[85],"this":[86,113],"often":[87],"conflicts":[88],"as":[93],"minimum":[94],"routes":[96],"create":[97],"congested":[98],"areas,":[99],"for":[100,209,239],"which":[101],"exact":[103],"cannot":[105],"be":[106,164],"realized":[107],"without":[108,166],"violating":[109],"design":[110],"rules.":[111],"In":[112],"work,":[114],"use":[116,236],"concept":[118],"pattern":[120,161,184,213,221],"develop":[123,216],"algorithms":[124,219,238],"guide":[126],"router":[128],"solution":[131],"minimizes":[133],"-":[136],"by":[137,205],"considering":[138],"both":[139,240],"coupling":[140,210],"and":[141,218,223,235,242],"wirelength-without":[142],"damaging":[143],"routability":[145,169,193],"The":[149,156,197],"paper":[150],"divided":[152],"into":[153],"two":[154,175],"parts.":[155],"first":[157],"part":[158,199,204],"demonstrates":[159],"can":[163],"used":[165],"affecting":[167],"We":[173,215],"propose":[174],"schemes":[176],"choose":[178],"set":[180],"nets":[182],"route.":[185],"Using":[186],"these":[187],"schemes,":[188],"show":[190],"not":[195],"hindered.":[196],"second":[198],"builds":[200],"previous":[203],"presenting":[206],"framework":[208],"reduction":[211],"using":[212],"theory":[217,234],"relating":[220],"coupling.":[224],"Additionally,":[225],"give":[227],"suggestions":[228],"how":[230],"extend":[232],"our":[233,237],"global":[241],"detailed":[243]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":6},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":5},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":6},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":7},{"year":2013,"cited_by_count":6},{"year":2012,"cited_by_count":6}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}