{"id":"https://openalex.org/W2153288389","doi":"https://doi.org/10.1109/tcad.1987.1270330","title":"Sensitivity Analysis for Device Design","display_name":"Sensitivity Analysis for Device Design","publication_year":1987,"publication_date":"1987-09-01","ids":{"openalex":"https://openalex.org/W2153288389","doi":"https://doi.org/10.1109/tcad.1987.1270330","mag":"2153288389"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1987.1270330","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270330","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083737379","display_name":"A. Gnudi","orcid":"https://orcid.org/0000-0002-2186-3468"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Gnudi","raw_affiliation_strings":["Dipartimento di Elettronica, Universit\u00e1 di Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Universit\u00e1 di Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037824516","display_name":"P. Ciampolini","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"P. Ciampolini","raw_affiliation_strings":["Dipartimento di Elettronica, Universit\u00e1 di Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Universit\u00e1 di Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102962030","display_name":"Renato Guerrieri","orcid":"https://orcid.org/0000-0003-4762-4905"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"R. Guerrieri","raw_affiliation_strings":["Dipartimento di Elettronica, Universit\u00e1 di Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Universit\u00e1 di Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045347874","display_name":"M. Rudan","orcid":"https://orcid.org/0000-0001-5485-7067"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Rudan","raw_affiliation_strings":["Dipartimento di Elettronica, Universit\u00e1 di Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Universit\u00e1 di Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027361765","display_name":"G. Baccarani","orcid":"https://orcid.org/0000-0001-7365-5495"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Baccarani","raw_affiliation_strings":["Dipartimento di Elettronica, Universit\u00e1 di Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Universit\u00e1 di Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.22723341,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"6","issue":"5","first_page":"879","last_page":"885"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sensitivity","display_name":"Sensitivity (control systems)","score":0.8236148357391357},{"id":"https://openalex.org/keywords/terminal","display_name":"Terminal (telecommunication)","score":0.5827602744102478},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5420109033584595},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.4834940731525421},{"id":"https://openalex.org/keywords/statistical-analysis","display_name":"Statistical analysis","score":0.4736933708190918},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33474573493003845},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2692355215549469},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22709250450134277},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.17383483052253723},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08081403374671936}],"concepts":[{"id":"https://openalex.org/C21200559","wikidata":"https://www.wikidata.org/wiki/Q7451068","display_name":"Sensitivity (control systems)","level":2,"score":0.8236148357391357},{"id":"https://openalex.org/C2779664074","wikidata":"https://www.wikidata.org/wiki/Q3518405","display_name":"Terminal (telecommunication)","level":2,"score":0.5827602744102478},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5420109033584595},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.4834940731525421},{"id":"https://openalex.org/C2986587452","wikidata":"https://www.wikidata.org/wiki/Q938438","display_name":"Statistical analysis","level":2,"score":0.4736933708190918},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33474573493003845},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2692355215549469},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22709250450134277},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.17383483052253723},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08081403374671936}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.1987.1270330","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270330","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W648216116","https://openalex.org/W1988190950","https://openalex.org/W2032743383","https://openalex.org/W2054954993","https://openalex.org/W2058853065","https://openalex.org/W2065139831","https://openalex.org/W2065725998","https://openalex.org/W2072656950","https://openalex.org/W2090070944","https://openalex.org/W2120553722","https://openalex.org/W2140496456","https://openalex.org/W2171450065","https://openalex.org/W2271921135","https://openalex.org/W2294268143","https://openalex.org/W2569133694","https://openalex.org/W4247629138","https://openalex.org/W4298132033"],"related_works":["https://openalex.org/W3211557223","https://openalex.org/W2007036916","https://openalex.org/W2120266540","https://openalex.org/W3015807911","https://openalex.org/W872563264","https://openalex.org/W2164087676","https://openalex.org/W4240867999","https://openalex.org/W2416728927","https://openalex.org/W4206528302","https://openalex.org/W108604697"],"abstract_inverted_index":{"In":[0],"this":[1,12],"paper":[2],"we":[3,14],"propose":[4],"a":[5],"sensitivity-analysis":[6],"technique":[7,44],"for":[8,91],"device":[9,21,34,96],"design.":[10,97],"By":[11],"method,":[13],"determine":[15],"the":[16,20,29,63,66,77,84],"linearized":[17],"variations":[18],"of":[19,65],"terminal":[22],"characteristics":[23],"following":[24],"some":[25],"change":[26],"either":[27],"in":[28,33,48,73],"impurity":[30],"distribution,":[31],"or":[32],"geometry,":[35],"such":[36],"as":[37,61],"channel":[38],"length":[39],"and":[40,55,68,94],"oxide":[41],"thickness.":[42],"This":[43],"has":[45],"been":[46],"implemented":[47],"our":[49],"general-purpose":[50],"two-dimensional":[51],"device-analysis":[52],"program":[53],"(HFIELDS)":[54],"proved":[56],"to":[57,75],"be":[58,88],"very":[59],"efficient,":[60],"only":[62],"assembly":[64],"RHS":[67],"one":[69],"back-substituton":[70],"is":[71,81],"required":[72],"order":[74],"achieve":[76],"final":[78],"result.":[79],"It":[80],"believed":[82],"that":[83],"present":[85],"method":[86],"can":[87],"profitably":[89],"used":[90],"both":[92],"deterministic":[93],"statistical":[95]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}