{"id":"https://openalex.org/W2035396884","doi":"https://doi.org/10.1109/tcad.1987.1270325","title":"Asymptotically Perfect Trivial Global Routing: A Stochastic Analysis","display_name":"Asymptotically Perfect Trivial Global Routing: A Stochastic Analysis","publication_year":1987,"publication_date":"1987-09-01","ids":{"openalex":"https://openalex.org/W2035396884","doi":"https://doi.org/10.1109/tcad.1987.1270325","mag":"2035396884"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1987.1270325","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270325","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083890565","display_name":"Gregory B. Sorkin","orcid":"https://orcid.org/0000-0003-4935-7820"},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]},{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"G.B. Sorkin","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, USA","IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]},{"raw_affiliation_string":"IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA","institution_ids":["https://openalex.org/I4210114115"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5083890565"],"corresponding_institution_ids":["https://openalex.org/I4210114115","https://openalex.org/I95457486"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.14725784,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"6","issue":"5","first_page":"820","last_page":"827"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/upper-and-lower-bounds","display_name":"Upper and lower bounds","score":0.7309304475784302},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7191016674041748},{"id":"https://openalex.org/keywords/row","display_name":"Row","score":0.6595871448516846},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6466735601425171},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5607917904853821},{"id":"https://openalex.org/keywords/row-and-column-spaces","display_name":"Row and column spaces","score":0.5421451330184937},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.5053523182868958},{"id":"https://openalex.org/keywords/function","display_name":"Function (biology)","score":0.49954915046691895},{"id":"https://openalex.org/keywords/fraction","display_name":"Fraction (chemistry)","score":0.4994382858276367},{"id":"https://openalex.org/keywords/routing-algorithm","display_name":"Routing algorithm","score":0.425730437040329},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.4244660437107086},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.37453150749206543},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.36803364753723145},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.36662185192108154},{"id":"https://openalex.org/keywords/routing-protocol","display_name":"Routing protocol","score":0.1255331039428711},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12353330850601196},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.09473523497581482},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.09405136108398438},{"id":"https://openalex.org/keywords/mathematical-analysis","display_name":"Mathematical analysis","score":0.08099493384361267}],"concepts":[{"id":"https://openalex.org/C77553402","wikidata":"https://www.wikidata.org/wiki/Q13222579","display_name":"Upper and lower bounds","level":2,"score":0.7309304475784302},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7191016674041748},{"id":"https://openalex.org/C135598885","wikidata":"https://www.wikidata.org/wiki/Q1366302","display_name":"Row","level":2,"score":0.6595871448516846},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6466735601425171},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5607917904853821},{"id":"https://openalex.org/C104140500","wikidata":"https://www.wikidata.org/wiki/Q2088159","display_name":"Row and column spaces","level":3,"score":0.5421451330184937},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.5053523182868958},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.49954915046691895},{"id":"https://openalex.org/C149629883","wikidata":"https://www.wikidata.org/wiki/Q660926","display_name":"Fraction (chemistry)","level":2,"score":0.4994382858276367},{"id":"https://openalex.org/C2984173633","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Routing algorithm","level":4,"score":0.425730437040329},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.4244660437107086},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.37453150749206543},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.36803364753723145},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.36662185192108154},{"id":"https://openalex.org/C104954878","wikidata":"https://www.wikidata.org/wiki/Q1648707","display_name":"Routing protocol","level":3,"score":0.1255331039428711},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12353330850601196},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.09473523497581482},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.09405136108398438},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.08099493384361267},{"id":"https://openalex.org/C178790620","wikidata":"https://www.wikidata.org/wiki/Q11351","display_name":"Organic chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C78458016","wikidata":"https://www.wikidata.org/wiki/Q840400","display_name":"Evolutionary biology","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tcad.1987.1270325","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270325","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:researchonline.lse.ac.uk:35567","is_oa":false,"landing_page_url":"https://orcid.org/0000-0003-4935-7820>","pdf_url":null,"source":{"id":"https://openalex.org/S4306401593","display_name":"London School of Economics and Political Science Research Online (London School of Economics and Political Science)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I909854389","host_organization_name":"London School of Economics and Political Science","host_organization_lineage":["https://openalex.org/I909854389"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":null,"raw_type":"PeerReviewed"},{"id":"pmh:oai:eprints.lse.ac.uk:35567","is_oa":false,"landing_page_url":"http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43","pdf_url":null,"source":{"id":"https://openalex.org/S4306401593","display_name":"London School of Economics and Political Science Research Online (London School of Economics and Political Science)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I909854389","host_organization_name":"London School of Economics and Political Science","host_organization_lineage":["https://openalex.org/I909854389"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"PeerReviewed"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Life below water","id":"https://metadata.un.org/sdg/14","score":0.8799999952316284}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1991530123","https://openalex.org/W2004759812","https://openalex.org/W2011786775","https://openalex.org/W2015540924","https://openalex.org/W2029853052","https://openalex.org/W2031904783","https://openalex.org/W2056883404","https://openalex.org/W2116683188"],"related_works":["https://openalex.org/W2313440505","https://openalex.org/W3123744736","https://openalex.org/W2137691148","https://openalex.org/W1505848319","https://openalex.org/W4281399881","https://openalex.org/W3166006430","https://openalex.org/W4281971614","https://openalex.org/W2049180840","https://openalex.org/W3121299875","https://openalex.org/W4214481814"],"abstract_inverted_index":{"A":[0,59],"two-dimensional":[1],"stochastic":[2],"model":[3,24],"of":[4,8,31,39,55,68,85,109,118,128,131],"the":[5,23,26,29,40,43,65,69,72,82,86,97,107,110,116,119,129,132],"global":[6],"wiring":[7,94],"a":[9,13,37,89,126],"VLSI":[10],"chip":[11,70,87,98],"in":[12,22],"standard-cell":[14],"or":[15],"sea-of-gates":[16],"design":[17],"style":[18],"is":[19,25,35,48,62,79,100,113,144,157],"defined;":[20],"prominent":[21],"property":[27],"that":[28,51,147],"probability":[30,149],"connecting":[32],"two":[33,57],"pins":[34],"solely":[36],"function":[38],"distance":[41],"between":[42],"cells":[44],"containing":[45],"them.":[46],"It":[47,143],"also":[49,145],"assumed":[50],"each":[52],"net":[53],"consists":[54],"just":[56],"pins.":[58],"lower":[60],"bound":[61,78],"placed":[63,80],"on":[64,81],"expected":[66,83],"size":[67,84,99,108,130,155],"with":[71,88,148],"best":[73],"possible":[74],"wiring.":[75],"An":[76],"upper":[77],"trivial":[90,120],"(all":[91],"randomly-oriented":[92],"\"L\"s)":[93],"scheme.":[95],"If":[96],"m":[101],"rows":[102],"by":[103],"n":[104],"columns":[105],"and":[106,121],"average":[111],"row":[112],"/overbar":[114,141,164],"\u03bc/":[115,142],"sizes":[117],"perfect":[122,133],"routings,":[123],"expressed":[124],"as":[125,137],"fraction":[127],"routing,":[134],"approaches":[135],"0":[136],"\u221a2":[138,161],"log":[139,162],"(n)/":[140],"shown":[146],"at":[150],"least":[151],"1":[152],"-":[153],"\u220a":[154],"increase":[156],"no":[158],"more":[159],"than":[160],"(mn/\u220a/":[163],"\u03bc/.":[165]},"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
