{"id":"https://openalex.org/W2048444690","doi":"https://doi.org/10.1109/tcad.1987.1270324","title":"Hierarchical Loose Routing for Gate Arrays","display_name":"Hierarchical Loose Routing for Gate Arrays","publication_year":1987,"publication_date":"1987-09-01","ids":{"openalex":"https://openalex.org/W2048444690","doi":"https://doi.org/10.1109/tcad.1987.1270324","mag":"2048444690"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1987.1270324","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270324","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029095426","display_name":"K. Winter","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119349","display_name":"Karlsruhe University of Education","ror":"https://ror.org/01t1kq612","country_code":"DE","type":"education","lineage":["https://openalex.org/I4210119349"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"K. Winter","raw_affiliation_strings":["University of Karlsruhe, Karlsruhe, Germany"],"affiliations":[{"raw_affiliation_string":"University of Karlsruhe, Karlsruhe, Germany","institution_ids":["https://openalex.org/I4210119349"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021721158","display_name":"D.A. Mlynski","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119349","display_name":"Karlsruhe University of Education","ror":"https://ror.org/01t1kq612","country_code":"DE","type":"education","lineage":["https://openalex.org/I4210119349"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"D.A. Mlynski","raw_affiliation_strings":["University of Karlsruhe, Karlsruhe, Germany"],"affiliations":[{"raw_affiliation_string":"University of Karlsruhe, Karlsruhe, Germany","institution_ids":["https://openalex.org/I4210119349"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5029095426"],"corresponding_institution_ids":["https://openalex.org/I4210119349"],"apc_list":null,"apc_paid":null,"fwci":1.36083756,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.81874545,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"6","issue":"5","first_page":"810","last_page":"819"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6886371374130249},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6557169556617737},{"id":"https://openalex.org/keywords/net","display_name":"Net (polyhedron)","score":0.556209146976471},{"id":"https://openalex.org/keywords/embedding","display_name":"Embedding","score":0.546038031578064},{"id":"https://openalex.org/keywords/spanning-tree","display_name":"Spanning tree","score":0.4671090841293335},{"id":"https://openalex.org/keywords/hierarchical-routing","display_name":"Hierarchical routing","score":0.4297233521938324},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42519962787628174},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.42508262395858765},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.35041701793670654},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3426215946674347},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.33642515540122986},{"id":"https://openalex.org/keywords/static-routing","display_name":"Static routing","score":0.2914387285709381},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.22952288389205933},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1884099841117859},{"id":"https://openalex.org/keywords/routing-protocol","display_name":"Routing protocol","score":0.1683664619922638},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16614198684692383},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.08723175525665283},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08167439699172974},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.06930360198020935}],"concepts":[{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6886371374130249},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6557169556617737},{"id":"https://openalex.org/C14166107","wikidata":"https://www.wikidata.org/wiki/Q253829","display_name":"Net (polyhedron)","level":2,"score":0.556209146976471},{"id":"https://openalex.org/C41608201","wikidata":"https://www.wikidata.org/wiki/Q980509","display_name":"Embedding","level":2,"score":0.546038031578064},{"id":"https://openalex.org/C64331007","wikidata":"https://www.wikidata.org/wiki/Q831672","display_name":"Spanning tree","level":2,"score":0.4671090841293335},{"id":"https://openalex.org/C177818476","wikidata":"https://www.wikidata.org/wiki/Q12878103","display_name":"Hierarchical routing","level":5,"score":0.4297233521938324},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42519962787628174},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.42508262395858765},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.35041701793670654},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3426215946674347},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.33642515540122986},{"id":"https://openalex.org/C204948658","wikidata":"https://www.wikidata.org/wiki/Q1119410","display_name":"Static routing","level":4,"score":0.2914387285709381},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.22952288389205933},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1884099841117859},{"id":"https://openalex.org/C104954878","wikidata":"https://www.wikidata.org/wiki/Q1648707","display_name":"Routing protocol","level":3,"score":0.1683664619922638},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16614198684692383},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.08723175525665283},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08167439699172974},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.06930360198020935},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.1987.1270324","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270324","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5199999809265137,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1655990431","https://openalex.org/W1979569488","https://openalex.org/W1982609842","https://openalex.org/W1987980734","https://openalex.org/W2020498688","https://openalex.org/W2036030013","https://openalex.org/W2043747057","https://openalex.org/W2062266989","https://openalex.org/W2144483873","https://openalex.org/W2168380797","https://openalex.org/W4242824706","https://openalex.org/W6661095006"],"related_works":["https://openalex.org/W2081900870","https://openalex.org/W2912321008","https://openalex.org/W2374925474","https://openalex.org/W2183306018","https://openalex.org/W2549990292","https://openalex.org/W2324368075","https://openalex.org/W2345479200","https://openalex.org/W2152063629","https://openalex.org/W4231567751","https://openalex.org/W4237042129"],"abstract_inverted_index":{"In":[0],"this":[1,60],"paper,":[2],"we":[3],"present":[4],"a":[5,23,34,55,65,72,80,87],"new,":[6],"quasi-parallel":[7,88],"approach":[8,82],"to":[9,86],"the":[10,27,69,115],"loose":[11,48,107],"routing":[12,49,97,108],"problem":[13,29],"for":[14,26,99],"gate":[15,118],"array":[16,119],"LSI":[17],"design.":[18],"It":[19,93],"is":[20,50,83,112],"based":[21],"on":[22,128],"new":[24],"modeling":[25],"decomposition":[28],"of":[30,41,44,54,68,74,90],"each":[31],"net":[32,36,61],"using":[33],"compact":[35],"graph":[37,62],"which":[38],"maps":[39],"sets":[40],"feed-throughs":[42],"instead":[43],"individual":[45],"ones.":[46],"The":[47,105],"done":[51],"by":[52,64],"calculation":[53],"minimum":[56],"spanning":[57],"tree":[58,70],"in":[59,114],"and":[63,77,123],"proper":[66],"embedding":[67,89],"as":[71],"set":[73],"single-channel":[75],"subnets":[76],"feed-throughs.":[78],"Moreover,":[79],"hierarchical":[81,106],"proposed,":[84],"leading":[85],"all":[91],"nets.":[92,104],"also":[94],"allows":[95],"different":[96],"priorities":[98],"single":[100],"connections":[101],"within":[102],"multiterminal":[103],"concept":[109],"presented":[110],"here":[111],"implemented":[113],"fully":[116],"integrated":[117],"design":[120,131],"system":[121],"MEGA":[122],"has":[124],"been":[125],"successfully":[126],"tested":[127],"several":[129],"industrial":[130],"examples.":[132]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}