{"id":"https://openalex.org/W1986780597","doi":"https://doi.org/10.1109/tcad.1987.1270320","title":"Fast Methods for Switch-Level Verification of MOS Circuits","display_name":"Fast Methods for Switch-Level Verification of MOS Circuits","publication_year":1987,"publication_date":"1987-09-01","ids":{"openalex":"https://openalex.org/W1986780597","doi":"https://doi.org/10.1109/tcad.1987.1270320","mag":"1986780597"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1987.1270320","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270320","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030462464","display_name":"Douglas S. Reeves","orcid":"https://orcid.org/0000-0002-1775-0639"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]},{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"education","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"D.S. Reeves","raw_affiliation_strings":["Department of Computer Science, Pennsylvania State University, USA","Dept. of Comput. Sci., North Carolina State Univ., Raleigh, NC, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Pennsylvania State University, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"Dept. of Comput. Sci., North Carolina State Univ., Raleigh, NC, USA#TAB#","institution_ids":["https://openalex.org/I137902535"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112796358","display_name":"M.J. Irwin","orcid":null},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.J. Irwin","raw_affiliation_strings":["Department of Computer Science, Pennsylvania State University, University Park, PA, USA","School of Electrical Engineering and Computer Science"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"School of Electrical Engineering and Computer Science","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5030462464"],"corresponding_institution_ids":["https://openalex.org/I130769515","https://openalex.org/I137902535"],"apc_list":null,"apc_paid":null,"fwci":3.1396,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.90233626,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":"6","issue":"5","first_page":"766","last_page":"779"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.9386770725250244},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7779695987701416},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5052652955055237},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5044022798538208},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.4724189043045044},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.44544684886932373},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4327494204044342},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.4250618815422058},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4245944321155548},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4210865795612335},{"id":"https://openalex.org/keywords/permission","display_name":"Permission","score":0.4205326735973358},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.41289931535720825},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.40959852933883667},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3698625862598419},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.36740660667419434},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3313658833503723},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.32097572088241577},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.31772246956825256},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.31734466552734375},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.26023852825164795},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.1726170778274536},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.17257347702980042},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10415303707122803},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09558770060539246},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08097437024116516}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.9386770725250244},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7779695987701416},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5052652955055237},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5044022798538208},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.4724189043045044},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.44544684886932373},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4327494204044342},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.4250618815422058},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4245944321155548},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4210865795612335},{"id":"https://openalex.org/C2779089604","wikidata":"https://www.wikidata.org/wiki/Q7169333","display_name":"Permission","level":2,"score":0.4205326735973358},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.41289931535720825},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.40959852933883667},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3698625862598419},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.36740660667419434},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3313658833503723},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32097572088241577},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.31772246956825256},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.31734466552734375},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.26023852825164795},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.1726170778274536},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.17257347702980042},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10415303707122803},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09558770060539246},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08097437024116516},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.1987.1270320","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270320","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W74317245","https://openalex.org/W186216482","https://openalex.org/W1487186769","https://openalex.org/W1520859699","https://openalex.org/W1588380009","https://openalex.org/W1926171971","https://openalex.org/W1967575124","https://openalex.org/W1975486750","https://openalex.org/W2011039300","https://openalex.org/W2014393101","https://openalex.org/W2032559236","https://openalex.org/W2059454390","https://openalex.org/W2063169916","https://openalex.org/W2080267935","https://openalex.org/W2082652314","https://openalex.org/W2109103805","https://openalex.org/W2147699841","https://openalex.org/W2149609054","https://openalex.org/W2294466096","https://openalex.org/W2594240710","https://openalex.org/W2798960321","https://openalex.org/W3139205562","https://openalex.org/W4233147043","https://openalex.org/W4248356462","https://openalex.org/W4285719527","https://openalex.org/W6602992328","https://openalex.org/W6635001764","https://openalex.org/W6792556425"],"related_works":["https://openalex.org/W4245336546","https://openalex.org/W2038511870","https://openalex.org/W2037756218","https://openalex.org/W2123076670","https://openalex.org/W1941005775","https://openalex.org/W3129822007","https://openalex.org/W2059633553","https://openalex.org/W2157541699","https://openalex.org/W2304374807","https://openalex.org/W2108495667"],"abstract_inverted_index":{"Simulation":[0],"of":[1,19,25,35,48,58,63,74,82,99,117],"hardware":[2],"is":[3,22,77,88,115],"a":[4,10,16,23,27,56,91,110],"commonly-used":[5],"method":[6,24],"for":[7,15,32],"demonstrating":[8],"that":[9],"circuit":[11,28,44,102],"design":[12,29],"will":[13,30],"work":[14,31],"restricted":[17],"set":[18],"inputs.":[20],"Verification":[21],"proving":[26],"all":[33],"combinations":[34],"input":[36],"values.":[37],"Switch-level":[38],"verification":[39,81,98],"works":[40],"directly":[41],"from":[42],"the":[43,67,75,97,118],"netlist.":[45],"The":[46],"performance":[47],"existing":[49],"switch-level":[50],"verifiers":[51],"has":[52],"been":[53,107],"improved":[54],"through":[55],"combination":[57],"techniques.":[59],"First,":[60],"efficient":[61],"methods":[62],"finding":[64],"paths":[65],"in":[66,90,109],"switch-graph":[68,76],"are":[69,125],"developed.":[70],"Secondly,":[71],"static":[72],"analysis":[73],"proposed":[78],"to":[79,94],"accelerate":[80],"sequential":[83],"logic.":[84],"Thirdly,":[85],"cell":[86],"replication":[87],"exploited":[89],"safe":[92],"way":[93],"make":[95],"possible":[96],"large":[100],"hierarchical":[101],"designs.":[103],"These":[104],"ideas":[105],"have":[106],"implemented":[108],"program":[111],"called":[112],"V,":[113],"which":[114],"part":[116],"Penn":[119],"State":[120],"Design":[121],"System.":[122],"Experimental":[123],"results":[124],"presented.":[126]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}