{"id":"https://openalex.org/W2028937844","doi":"https://doi.org/10.1109/tcad.1987.1270307","title":"A Methodology for Optimal Test Structure Design for Statistical Process Characterization and Diagnosis","display_name":"A Methodology for Optimal Test Structure Design for Statistical Process Characterization and Diagnosis","publication_year":1987,"publication_date":"1987-07-01","ids":{"openalex":"https://openalex.org/W2028937844","doi":"https://doi.org/10.1109/tcad.1987.1270307","mag":"2028937844"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1987.1270307","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270307","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077076818","display_name":"Ihao Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ihao Chen","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008759589","display_name":"Andrzej J. Strojwas","orcid":"https://orcid.org/0000-0001-9549-0302"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A.J. Strojwas","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5077076818"],"corresponding_institution_ids":["https://openalex.org/I74973139"],"apc_list":null,"apc_paid":null,"fwci":2.3028,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.89021691,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"6","issue":"4","first_page":"592","last_page":"600"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.6142902970314026},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5312597155570984},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.516586184501648},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4904806315898895},{"id":"https://openalex.org/keywords/statistical-hypothesis-testing","display_name":"Statistical hypothesis testing","score":0.48243722319602966},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.44133487343788147},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.4150940179824829},{"id":"https://openalex.org/keywords/test-method","display_name":"Test method","score":0.4103090167045593},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2727399468421936},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18472957611083984},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.17114531993865967},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.06620427966117859}],"concepts":[{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.6142902970314026},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5312597155570984},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.516586184501648},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4904806315898895},{"id":"https://openalex.org/C87007009","wikidata":"https://www.wikidata.org/wiki/Q210832","display_name":"Statistical hypothesis testing","level":2,"score":0.48243722319602966},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.44133487343788147},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.4150940179824829},{"id":"https://openalex.org/C132519959","wikidata":"https://www.wikidata.org/wiki/Q3077373","display_name":"Test method","level":2,"score":0.4103090167045593},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2727399468421936},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18472957611083984},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.17114531993865967},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.06620427966117859},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.1987.1270307","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270307","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1574542534","https://openalex.org/W1978971571","https://openalex.org/W1983843281","https://openalex.org/W1987368972","https://openalex.org/W2017209251","https://openalex.org/W2058853065","https://openalex.org/W2059419335","https://openalex.org/W2064484730","https://openalex.org/W2072656950","https://openalex.org/W2170303383","https://openalex.org/W2791060502","https://openalex.org/W4213188785"],"related_works":["https://openalex.org/W2217098757","https://openalex.org/W2088771128","https://openalex.org/W2263373136","https://openalex.org/W2796085262","https://openalex.org/W190245591","https://openalex.org/W1650778624","https://openalex.org/W2545385022","https://openalex.org/W2364813009","https://openalex.org/W4252286421","https://openalex.org/W2048327065"],"abstract_inverted_index":{"This":[0,82],"paper":[1],"presents":[2],"a":[3,29,44,99],"general":[4],"methodology":[5,83],"for":[6,52,62,89],"designing":[7],"optimal":[8],"test":[9,26,31,38,68,71],"structures":[10],"and":[11,70],"their":[12],"applications":[13],"to":[14,43,98],"characterize":[15],"the":[16,64,92],"process":[17,48],"fluctuations":[18],"inherent":[19],"in":[20,35],"IC":[21],"manufacturing.":[22],"A":[23],"set":[24],"of":[25,47,67,91],"structures,":[27,69],"including":[28],"novel":[30],"structure,":[32],"is":[33,41,56,84],"presented":[34],"which":[36],"each":[37],"structure":[39],"parameter":[40,54],"sensitive":[42],"minimal":[45],"number":[46],"parameters.":[49],"The":[50],"procedure":[51],"device":[53,59],"extraction":[55],"described.":[57],"Optimal":[58],"dimensions,":[60],"criteria":[61],"choosing":[63],"sample":[65],"sizes":[66],"chips":[72],"are":[73],"also":[74],"determined":[75],"based":[76],"upon":[77],"statistical":[78,93],"hypothesis":[79],"testing":[80],"techniques.":[81],"illustrated":[85],"by":[86],"an":[87],"application":[88],"tuning":[90],"process/device":[94],"simulator":[95],"FABRICS":[96],"II":[97],"typical":[100],"NMOS":[101],"fabrication":[102],"process.":[103]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2026-04-28T14:05:53.105641","created_date":"2025-10-10T00:00:00"}
