{"id":"https://openalex.org/W2137326236","doi":"https://doi.org/10.1109/tcad.1987.1270295","title":"Derivation of Signal Flow Direction in MOS VLSI","display_name":"Derivation of Signal Flow Direction in MOS VLSI","publication_year":1987,"publication_date":"1987-05-01","ids":{"openalex":"https://openalex.org/W2137326236","doi":"https://doi.org/10.1109/tcad.1987.1270295","mag":"2137326236"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1987.1270295","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270295","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050207942","display_name":"Norman P. Jouppi","orcid":"https://orcid.org/0000-0003-1765-1929"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"N. Jouppi","raw_affiliation_strings":["Computer Systems Laboratory, University of Stanford, Stanford, CA, USA","Western Research Laboratory, Digital Equipment Corporation, Palo Alto, CA, USA"],"affiliations":[{"raw_affiliation_string":"Computer Systems Laboratory, University of Stanford, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]},{"raw_affiliation_string":"Western Research Laboratory, Digital Equipment Corporation, Palo Alto, CA, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5050207942"],"corresponding_institution_ids":["https://openalex.org/I97018004"],"apc_list":null,"apc_paid":null,"fwci":6.8022,"has_fulltext":false,"cited_by_count":49,"citation_normalized_percentile":{"value":0.97264323,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"6","issue":"3","first_page":"480","last_page":"490"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.7029933929443359},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6419475078582764},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.6229428648948669},{"id":"https://openalex.org/keywords/signal-flow-graph","display_name":"Signal-flow graph","score":0.619036853313446},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6140362620353699},{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.5697640180587769},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5669719576835632},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5536959171295166},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5494992136955261},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5168259739875793},{"id":"https://openalex.org/keywords/flow","display_name":"Flow (mathematics)","score":0.46879658102989197},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4269741177558899},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4163168668746948},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.32763826847076416},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2220115065574646},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2037152647972107},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19794344902038574},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15047433972358704},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.07177266478538513}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.7029933929443359},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6419475078582764},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.6229428648948669},{"id":"https://openalex.org/C166501922","wikidata":"https://www.wikidata.org/wiki/Q1786523","display_name":"Signal-flow graph","level":2,"score":0.619036853313446},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6140362620353699},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.5697640180587769},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5669719576835632},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5536959171295166},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5494992136955261},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5168259739875793},{"id":"https://openalex.org/C38349280","wikidata":"https://www.wikidata.org/wiki/Q1434290","display_name":"Flow (mathematics)","level":2,"score":0.46879658102989197},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4269741177558899},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4163168668746948},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.32763826847076416},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2220115065574646},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2037152647972107},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19794344902038574},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15047433972358704},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.07177266478538513},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.1987.1270295","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270295","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5099999904632568,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1509095758","https://openalex.org/W1542308253","https://openalex.org/W1572101818","https://openalex.org/W1982108374","https://openalex.org/W2055388012","https://openalex.org/W2056292591","https://openalex.org/W2106918565","https://openalex.org/W4235374322","https://openalex.org/W4235586079"],"related_works":["https://openalex.org/W2217098757","https://openalex.org/W2088771128","https://openalex.org/W2263373136","https://openalex.org/W2796085262","https://openalex.org/W190245591","https://openalex.org/W1650778624","https://openalex.org/W2545385022","https://openalex.org/W2022549222","https://openalex.org/W2082944690","https://openalex.org/W2035871485"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"two":[3],"sets":[4],"of":[5,11,25,44,62,70,85],"rules":[6,58,95],"for":[7,21],"deriving":[8],"the":[9,60,71],"direction":[10,61],"signal":[12,63,87],"flow":[13,64],"in":[14,28,73,78,89],"MOS":[15],"circuits.":[16],"The":[17,47,83],"first":[18],"set":[19,49],"works":[20],"a":[22,90],"wide":[23],"range":[24],"circuit":[26,45],"designs":[27],"both":[29],"nMOS":[30],"and":[31,41,52,93],"CMOS":[32],"technologies":[33],"because":[34],"it":[35],"is":[36,97],"based":[37],"on":[38],"basic":[39],"electrical":[40,94],"logical":[42],"principles":[43],"design.":[46],"second":[48],"contains":[50],"design":[51,81],"technology":[53],"specific":[54],"heuristics.":[55],"Together":[56],"these":[57],"yield":[59],"through":[65],"more":[66],"than":[67],"99.9":[68],"percent":[69],"transistors":[72],"four":[74,79],"VLSI":[75],"chips":[76],"constructed":[77],"different":[80],"styles.":[82],"application":[84],"derived":[86],"directions":[88],"timing":[91],"verifier":[92],"checker":[96],"also":[98],"discussed":[99]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}