{"id":"https://openalex.org/W2039198650","doi":"https://doi.org/10.1109/tcad.1987.1270281","title":"A Practical CAD System Application for Full Custom VLSI Microcomputer Chips","display_name":"A Practical CAD System Application for Full Custom VLSI Microcomputer Chips","publication_year":1987,"publication_date":"1987-05-01","ids":{"openalex":"https://openalex.org/W2039198650","doi":"https://doi.org/10.1109/tcad.1987.1270281","mag":"2039198650"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1987.1270281","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270281","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063487092","display_name":"A. Kurosawa","orcid":null},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"A. Kurosawa","raw_affiliation_strings":["NEC Corporation Limited, Kawasaki, Japan"],"affiliations":[{"raw_affiliation_string":"NEC Corporation Limited, Kawasaki, Japan","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016343542","display_name":"Kazuhiko Yamada","orcid":"https://orcid.org/0000-0003-4658-346X"},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Yamada","raw_affiliation_strings":["NEC Corporation Limited, Kawasaki, Japan"],"affiliations":[{"raw_affiliation_string":"NEC Corporation Limited, Kawasaki, Japan","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058743221","display_name":"Aritoyo Kishimoto","orcid":null},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"A. Kishimoto","raw_affiliation_strings":["NEC Corporation Limited, Kawasaki, Japan"],"affiliations":[{"raw_affiliation_string":"NEC Corporation Limited, Kawasaki, Japan","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101396802","display_name":"K. Mori","orcid":"https://orcid.org/0000-0003-2140-295X"},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Mori","raw_affiliation_strings":["NEC Corporation Limited, Kawasaki, Japan"],"affiliations":[{"raw_affiliation_string":"NEC Corporation Limited, Kawasaki, Japan","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057068098","display_name":"Nobuyuki Nishiguchi","orcid":null},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"N. Nishiguchi","raw_affiliation_strings":["NEC Corporation Limited, Kawasaki, Japan"],"affiliations":[{"raw_affiliation_string":"NEC Corporation Limited, Kawasaki, Japan","institution_ids":["https://openalex.org/I118347220"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5063487092"],"corresponding_institution_ids":["https://openalex.org/I118347220"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.15252798,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"6","issue":"3","first_page":"364","last_page":"373"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7255901098251343},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5764707326889038},{"id":"https://openalex.org/keywords/microcomputer","display_name":"Microcomputer","score":0.569121241569519},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4849134087562561},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.48053058981895447},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.47854501008987427},{"id":"https://openalex.org/keywords/cad","display_name":"CAD","score":0.4741078019142151},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.4677583873271942},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.46200913190841675},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.44285792112350464},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4356438219547272},{"id":"https://openalex.org/keywords/design-layout-record","display_name":"Design layout record","score":0.42368319630622864},{"id":"https://openalex.org/keywords/ic-layout-editor","display_name":"IC layout editor","score":0.41909271478652954},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41467660665512085},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4009488821029663},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36467260122299194},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.31725913286209106},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2896135747432709},{"id":"https://openalex.org/keywords/engineering-drawing","display_name":"Engineering drawing","score":0.23779264092445374},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.1959696114063263},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.14221850037574768},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.11519262194633484}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7255901098251343},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5764707326889038},{"id":"https://openalex.org/C132090242","wikidata":"https://www.wikidata.org/wiki/Q32738","display_name":"Microcomputer","level":3,"score":0.569121241569519},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4849134087562561},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.48053058981895447},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.47854501008987427},{"id":"https://openalex.org/C194789388","wikidata":"https://www.wikidata.org/wiki/Q17855283","display_name":"CAD","level":2,"score":0.4741078019142151},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4677583873271942},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.46200913190841675},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.44285792112350464},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4356438219547272},{"id":"https://openalex.org/C179145894","wikidata":"https://www.wikidata.org/wiki/Q5264353","display_name":"Design layout record","level":5,"score":0.42368319630622864},{"id":"https://openalex.org/C5546195","wikidata":"https://www.wikidata.org/wiki/Q5969842","display_name":"IC layout editor","level":5,"score":0.41909271478652954},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41467660665512085},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4009488821029663},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36467260122299194},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.31725913286209106},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2896135747432709},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.23779264092445374},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.1959696114063263},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.14221850037574768},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.11519262194633484},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.1987.1270281","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270281","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5899999737739563}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1516927582","https://openalex.org/W1974734591","https://openalex.org/W1977040987","https://openalex.org/W1992273002","https://openalex.org/W2007755488","https://openalex.org/W2091495490","https://openalex.org/W2116580823","https://openalex.org/W2404136673","https://openalex.org/W4247720568","https://openalex.org/W4249985154","https://openalex.org/W4255205277","https://openalex.org/W6630954852","https://openalex.org/W6643919130","https://openalex.org/W6648342409","https://openalex.org/W6713945192"],"related_works":["https://openalex.org/W2091329789","https://openalex.org/W162881505","https://openalex.org/W2376028644","https://openalex.org/W2357425846","https://openalex.org/W2376726667","https://openalex.org/W583900352","https://openalex.org/W1568098132","https://openalex.org/W2138342018","https://openalex.org/W2125213949","https://openalex.org/W2154007719"],"abstract_inverted_index":{"This":[0,97],"paper":[1],"presents":[2],"a":[3,51,62,119,193,210,216,231],"practical":[4],"CAD":[5,20],"system":[6,21],"application":[7],"for":[8,92,156,186],"layout":[9,26,46,56,67,85,116],"and":[10,36,47,74,79,90,94],"verification,":[11],"resulting":[12],"in":[13,61,180,230],"producible":[14],"full-cutom":[15],"VLSI":[16,233],"microcomputer":[17,234],"chips.":[18],"The":[19,66,128,159,190,206],"supports":[22,50],"three":[23,163],"design":[24,164,184],"methodologies--symbolic":[25],"mixed":[27],"with":[28,58],"mask":[29],"level":[30],"layout,":[31],"compaction":[32,195],"as":[33],"an":[34],"optimizer,":[35],"fully":[37],"automated":[38],"verification.":[39],"For":[40,77],"the":[41,44,82,101,110,145,181,222],"area":[42],"optimization,":[43,81],"symbolic":[45,75],"compactor":[48,83],"subsystem":[49,130],"flexible":[52],"description":[53],"of":[54,135,144,161,237],"orthogonal":[55],"patterns":[57,68],"arbitrary":[59],"dimensions":[60],"loose":[63],"placement":[64],"manner.":[65],"include":[69],"path":[70],"data,":[71,73,86],"polygonal":[72],"cells.":[76],"power":[78],"delay":[80],"compacts":[84],"decreasing":[87],"both":[88],"resistance":[89],"capacitance":[91],"wires":[93],"ion-implanted":[95],"layers.":[96],"feature":[98,143],"is":[99,149,173,192,221],"pioneering":[100],"new":[102],"generation":[103],"compactor.":[104],"Emphasis":[105],"should":[106],"be":[107],"put":[108],"on":[109,209],"fact":[111],"that":[112,125,150,203],"it":[113,151],"can":[114,131],"compact":[115],"data":[117],"to":[118],"format":[120],"10-15":[121],"percent":[122],"smaller":[123,197],"than":[124,138,178,202,215,239],"accomplished":[126,229],"manually.":[127],"verification":[129],"detect":[132],"all":[133],"kinds":[134],"errors,":[136],"more":[137,177,214,238],"30":[139],"items.":[140],"A":[141],"novel":[142],"electrical":[146],"rule":[147],"check":[148],"investigates":[152],"complementary":[153],"logic":[154],"errors":[155],"CMOS":[157],"circuits.":[158],"synergy":[160],"those":[162],"methodologies":[165],"has":[166,227],"brought":[167],"about":[168],"several":[169],"significant":[170],"advantages.":[171],"One":[172],"manpower":[174],"reduction":[175],"by":[176,198],"half,":[179],"most":[182],"complicated":[183],"process":[185],"unique":[187],"random":[188],"logic.":[189],"other":[191],"1600-transistors":[194],"output,":[196],"365":[199],"mils/sup":[200],"2/":[201],"manually":[204],"compacted.":[205],"circuit":[207],"implementation":[208],"chip":[211,235],"works":[212],"at":[213],"15-MHz":[217],"clock":[218],"rate.":[219],"Another":[220],"first":[223],"silicon":[224],"success.":[225],"It":[226],"been":[228],"full-custom":[232],"consisting":[236],"100":[240],"000":[241],"transistors.":[242]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}