{"id":"https://openalex.org/W2116939489","doi":"https://doi.org/10.1109/tcad.1987.1270280","title":"Partitioning and Placement Technique for CMOS Gate Arrays","display_name":"Partitioning and Placement Technique for CMOS Gate Arrays","publication_year":1987,"publication_date":"1987-05-01","ids":{"openalex":"https://openalex.org/W2116939489","doi":"https://doi.org/10.1109/tcad.1987.1270280","mag":"2116939489"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1987.1270280","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270280","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108789565","display_name":"G. Odawara","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"G. Odawara","raw_affiliation_strings":["Department of Precision Engineering, Faculty of Engineering, University of Tokyo, Bunkyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Precision Engineering, Faculty of Engineering, University of Tokyo, Bunkyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046459828","display_name":"T. Hiraide","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Hiraide","raw_affiliation_strings":["Department of Precision Engineering, Faculty of Engineering, University of Tokyo, Bunkyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Precision Engineering, Faculty of Engineering, University of Tokyo, Bunkyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062517680","display_name":"O. Nishina","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"O. Nishina","raw_affiliation_strings":["Department of Precision Engineering, Faculty of Engineering, University of Tokyo, Bunkyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Precision Engineering, Faculty of Engineering, University of Tokyo, Bunkyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5108789565"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":25,"citation_normalized_percentile":{"value":0.21894161,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"6","issue":"3","first_page":"355","last_page":"363"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.6527130603790283},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6404445767402649},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6101912260055542},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.49497050046920776},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.45675286650657654},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45264604687690735},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.43747708201408386},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39322298765182495},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.32809728384017944},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.32075774669647217},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.24615126848220825},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.24549511075019836},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.22560715675354004},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21146929264068604},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20873519778251648},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13456609845161438}],"concepts":[{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.6527130603790283},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6404445767402649},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6101912260055542},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.49497050046920776},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.45675286650657654},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45264604687690735},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.43747708201408386},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39322298765182495},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.32809728384017944},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.32075774669647217},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.24615126848220825},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.24549511075019836},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.22560715675354004},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21146929264068604},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20873519778251648},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13456609845161438},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.1987.1270280","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270280","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1970296212","https://openalex.org/W1971803706","https://openalex.org/W1987029304","https://openalex.org/W2004229681","https://openalex.org/W2022678043","https://openalex.org/W2042766277","https://openalex.org/W2110514755","https://openalex.org/W2141523221","https://openalex.org/W2152063629","https://openalex.org/W2161455936","https://openalex.org/W2222512263","https://openalex.org/W3142390297","https://openalex.org/W4230952265","https://openalex.org/W4231567751","https://openalex.org/W4234113102","https://openalex.org/W4245574458","https://openalex.org/W4255037654"],"related_works":["https://openalex.org/W1597620877","https://openalex.org/W2163511129","https://openalex.org/W2155675690","https://openalex.org/W2185927297","https://openalex.org/W2135463389","https://openalex.org/W2111751849","https://openalex.org/W1999442455","https://openalex.org/W2167755864","https://openalex.org/W4249900664","https://openalex.org/W2995132887"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"an":[3],"automatic":[4],"partitioning":[5,50,83],"and":[6,21,33,40,64,97],"placement":[7,47,86,96],"system":[8],"for":[9,112],"CMOS":[10],"gate":[11],"arrays":[12],"utilizing":[13],"two":[14,54],"different":[15],"kinds":[16],"of":[17,61,81],"data:":[18],"circuit":[19,26,75],"structure":[20,32,36],"hierarchical":[22],"design":[23],"data.":[24],"Characteristic":[25],"structures":[27],"such":[28],"as":[29],"the":[30,34,46,58,65,68,73,82,85,107],"bus":[31],"iterative":[35],"are":[37],"automatically":[38],"extracted":[39],"handled":[41],"like":[42],"single":[43],"cells":[44],"in":[45],"process.":[48],"The":[49],"process":[51],"has":[52,103],"employed":[53],"processes:":[55,94],"one":[56],"is":[57,67,88,110],"bottom-up":[59],"extraction":[60],"these":[62],"structures,":[63],"other":[66],"top-down":[69],"process,":[70],"which":[71],"divides":[72],"given":[74],"into":[76],"several":[77],"subcircuits.":[78],"Making":[79],"use":[80],"results,":[84],"program":[87],"also":[89],"carried":[90],"out":[91],"by":[92],"two-level":[93],"subcircuit-level":[95],"cell-level":[98],"placement.":[99],"Through":[100],"experiments,":[101],"it":[102],"been":[104],"proved":[105],"that":[106],"proposed":[108],"technique":[109],"effective":[111],"attaining":[113],"better":[114],"layout":[115],"results.":[116]},"counts_by_year":[{"year":2019,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
