{"id":"https://openalex.org/W1986384065","doi":"https://doi.org/10.1109/tcad.1987.1270275","title":"A Silicon Compiler System Based on Asynchronous Architecture","display_name":"A Silicon Compiler System Based on Asynchronous Architecture","publication_year":1987,"publication_date":"1987-05-01","ids":{"openalex":"https://openalex.org/W1986384065","doi":"https://doi.org/10.1109/tcad.1987.1270275","mag":"1986384065"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1987.1270275","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270275","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072091635","display_name":"M. Hirayama","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"M. Hirayama","raw_affiliation_strings":["Central Research Laboratory, Mitsubishi Electric Corporation Limited, Japan","Central Research Laboratory, Mitsubishi Electric Corporation, Amagasaki, Japan"],"affiliations":[{"raw_affiliation_string":"Central Research Laboratory, Mitsubishi Electric Corporation Limited, Japan","institution_ids":["https://openalex.org/I4210133125"]},{"raw_affiliation_string":"Central Research Laboratory, Mitsubishi Electric Corporation, Amagasaki, Japan","institution_ids":["https://openalex.org/I4210133125"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5072091635"],"corresponding_institution_ids":["https://openalex.org/I4210133125"],"apc_list":null,"apc_paid":null,"fwci":0.8822,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.76350093,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"6","issue":"3","first_page":"297","last_page":"304"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9927999973297119,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.8679013848304749},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8537153005599976},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7532662153244019},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7165433764457703},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6303005218505859},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4715452492237091},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4590330421924591},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.31277984380722046}],"concepts":[{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.8679013848304749},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8537153005599976},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7532662153244019},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7165433764457703},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6303005218505859},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4715452492237091},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4590330421924591},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.31277984380722046},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.1987.1270275","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270275","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4399999976158142}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1504561502","https://openalex.org/W1967575124","https://openalex.org/W2004045008","https://openalex.org/W2081234028","https://openalex.org/W2135461915","https://openalex.org/W3144025793","https://openalex.org/W4249925044"],"related_works":["https://openalex.org/W3096456556","https://openalex.org/W4240253816","https://openalex.org/W2116677773","https://openalex.org/W2169584677","https://openalex.org/W2049402143","https://openalex.org/W2098218272","https://openalex.org/W2134640991","https://openalex.org/W3027318491","https://openalex.org/W1979789826","https://openalex.org/W1986774039"],"abstract_inverted_index":{"As":[0],"one":[1],"of":[2,11,16,35,46,78,98,109,130,151,178,187,197],"the":[3,8,14,30,36,43,47,75,79,103,110,126,131,135,145,149,165,175,179,185,190,198],"most":[4],"promising":[5],"approaches":[6],"for":[7,58,62],"automatic":[9],"generation":[10],"VLSI":[12,48,60,90],"chips,":[13],"concept":[15],"\"silicon":[17],"compilers\"":[18],"was":[19],"presented.":[20],"A":[21,89],"silicon":[22,86,122,166],"compiler":[23,80,87,123,167],"is":[24,112,161],"a":[25,54,85,195],"software":[26],"system":[27,124,168],"which":[28,101,173,201],"accepts":[29,125],"behavioral":[31],"or":[32],"functional":[33,128,176],"description":[34,177],"chip":[37,64,91,111,180],"and":[38,81,140,181,189,193],"directly":[39,141],"translates":[40,142],"it":[41,143,160,184],"to":[42,52,144,163],"layout":[44,146],"patterns":[45,147],"masks.":[49],"In":[50],"order":[51],"realize":[53,164],"design":[55],"automation":[56],"aid":[57],"full-custom":[59],"chips":[61],"nonprofessional":[63],"designers":[65],"such":[66],"as":[67,74],"programmers,":[68],"we":[69],"have":[70,82],"selected":[71],"asynchronous":[72,99,199],"architecture":[73,95,158],"target":[76],"model":[77,96],"been":[83],"developing":[84],"system.":[88],"based":[92],"on":[93],"this":[94],"consists":[97],"modules":[100,200],"hold":[102],"control":[104,191],"information":[105,192],"internally.":[106],"The":[107,121],"behavior":[108],"controlled":[113],"only":[114],"by":[115,134],"local":[116],"communication":[117],"among":[118],"these":[119],"modules.":[120],"purely":[127],"specifications":[129],"chip,":[132],"written":[133],"hardware":[136],"specification":[137],"language":[138],"ISPC,":[139],"in":[148],"form":[150],"CIF":[152],"codes.":[153],"By":[154],"selecting":[155],"an":[156],"effective":[157],"model,":[159],"possible":[162],"through":[169,194],"simple":[170],"translation":[171],"programs":[172],"analyze":[174],"extract":[182],"from":[183],"configuration":[186],"components":[188],"library":[196],"are":[202],"generally":[203],"defined":[204],"with":[205],"suitable":[206],"parameters.":[207]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
