{"id":"https://openalex.org/W1970090074","doi":"https://doi.org/10.1109/tcad.1987.1270255","title":"Network Partitioning and Ordering for MOS VLSI Circuits","display_name":"Network Partitioning and Ordering for MOS VLSI Circuits","publication_year":1987,"publication_date":"1987-01-01","ids":{"openalex":"https://openalex.org/W1970090074","doi":"https://doi.org/10.1109/tcad.1987.1270255","mag":"1970090074"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1987.1270255","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270255","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112780826","display_name":"Vasant B. Rao","orcid":null},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"V.B. Rao","raw_affiliation_strings":["Coordinated Science Laboratory, University of Illinois, Urbana, IL, USA","[Coordinated Science Laboratory, University of Illinois, Urbana, IL, USA]"],"affiliations":[{"raw_affiliation_string":"Coordinated Science Laboratory, University of Illinois, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]},{"raw_affiliation_string":"[Coordinated Science Laboratory, University of Illinois, Urbana, IL, USA]","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111888059","display_name":"T.N. Trick","orcid":null},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"T.N. Trick","raw_affiliation_strings":["Coordinated Science Laboratory, University of Illinois, Urbana, IL, USA","[Coordinated Science Laboratory, University of Illinois, Urbana, IL, USA]"],"affiliations":[{"raw_affiliation_string":"Coordinated Science Laboratory, University of Illinois, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]},{"raw_affiliation_string":"[Coordinated Science Laboratory, University of Illinois, Urbana, IL, USA]","institution_ids":["https://openalex.org/I157725225"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5112780826"],"corresponding_institution_ids":["https://openalex.org/I157725225"],"apc_list":null,"apc_paid":null,"fwci":1.5698,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.80049679,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"6","issue":"1","first_page":"128","last_page":"144"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6871151924133301},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6732507944107056},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6120128035545349},{"id":"https://openalex.org/keywords/partition","display_name":"Partition (number theory)","score":0.6074019074440002},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5959494113922119},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.495644211769104},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.47118639945983887},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.455271452665329},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.42903265357017517},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.41455209255218506},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3376997113227844},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.32689690589904785},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18954378366470337},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1627430021762848},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13995331525802612},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12969306111335754},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11199846863746643}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6871151924133301},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6732507944107056},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6120128035545349},{"id":"https://openalex.org/C42812","wikidata":"https://www.wikidata.org/wiki/Q1082910","display_name":"Partition (number theory)","level":2,"score":0.6074019074440002},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5959494113922119},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.495644211769104},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.47118639945983887},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.455271452665329},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.42903265357017517},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.41455209255218506},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3376997113227844},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.32689690589904785},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18954378366470337},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1627430021762848},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13995331525802612},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12969306111335754},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11199846863746643},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.1987.1270255","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1987.1270255","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W15412619","https://openalex.org/W606008011","https://openalex.org/W1482973734","https://openalex.org/W1520859699","https://openalex.org/W1533237582","https://openalex.org/W1546202437","https://openalex.org/W1655990431","https://openalex.org/W1825320825","https://openalex.org/W1981235568","https://openalex.org/W1984588379","https://openalex.org/W2011039300","https://openalex.org/W2024073620","https://openalex.org/W2034468751","https://openalex.org/W2059454390","https://openalex.org/W2118382442","https://openalex.org/W2128326790","https://openalex.org/W4234561472","https://openalex.org/W4237529192","https://openalex.org/W4241855679","https://openalex.org/W6631908527"],"related_works":["https://openalex.org/W4283025278","https://openalex.org/W2082432309","https://openalex.org/W817174743","https://openalex.org/W4254559750","https://openalex.org/W2998315020","https://openalex.org/W3016208414","https://openalex.org/W2050492524","https://openalex.org/W2104790384","https://openalex.org/W4254068099","https://openalex.org/W1976665945"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"the":[3,44,54,60,89,104,114,131,167,171,201,210,218,236],"algorithms":[4],"used":[5],"in":[6,29,77,107,170,203,209],"a":[7,30,78,145,177,190,196,204,223,228],"presimulation":[8],"phase":[9],"to":[10,23,48,53,58,81,95,130,189],"partition":[11],"an":[12,123],"MOS":[13],"digital":[14],"network":[15,45,173,205,225],"into":[16,65],"various":[17,168],"special":[18,247],"subnetworks":[19,26],"(or":[20],"blocks)":[21],"and":[22,67,161,176,186],"order":[24],"these":[25],"for":[27,139,149,199,244,260],"processing":[28,150,200],"switch-level":[31],"timing":[32],"simulator":[33],"such":[34,141],"as":[35],"MOSTIM":[36],"[1].":[37],"A":[38,100,159],"transistor-level":[39],"SPICE2-type":[40],"[3]":[41],"description":[42],"of":[43,62,116,164,212,215,222],"is":[46,57,111,122,127,147,174,179,193,206,232],"assumed":[47],"be":[49],"provided.":[50],"The":[51,70,119,133,252],"key":[52],"partitioning":[55,105,120],"strategy":[56],"divide":[59],"set":[61],"enhancement":[63,117],"transistors":[64,72,91],"driver":[66,71],"pass":[68,90,97],"transistors.":[69,118],"are":[73,92,136,157,241,256],"then":[74,137,242,257],"grouped":[75,93],"together":[76,94],"de-connected":[79],"sense":[80],"form":[82,96,214],"multiple-input":[83],"single-output":[84],"combinatorial":[85],"logic":[86],"blocks,":[87,239],"while":[88],"transistor":[98],"blocks.":[99,219],"graph":[101],"algorithm":[102,231],"performs":[103],"step":[106,121],"computation":[108],"time":[109,230],"that":[110,126,195,234],"linear":[112,229],"with":[113,226],"number":[115],"automatic":[124],"process":[125],"completely":[128],"transparent":[129],"user.":[132],"partitioned":[134,172,224],"blocks":[135,169,185,202],"ordered":[138,259],"simulation":[140,245],"that,":[142],"whenever":[143],"possible,":[144],"block":[146],"scheduled":[148],"only":[151,208],"after":[152],"all":[153],"its":[154],"input":[155],"waveforms":[156],"known.":[158],"clear":[160],"precise":[162],"notion":[163],"feedback":[165,182,187,216],"among":[166,183,217],"introduced,":[175],"distinction":[178],"made":[180],"between":[181],"different":[184],"internal":[188],"block.":[191],"It":[192],"shown":[194],"good":[197],"ordering":[198],"possible":[207],"absence":[211],"any":[213],"In":[220],"case":[221],"feedback,":[227],"presented":[233],"detects":[235],"strongly":[237,253],"connected":[238,254],"which":[240],"flagged":[243],"using":[246],"dynamic":[248],"windowing":[249],"techniques":[250],"[4].":[251],"components":[255],"topologically":[258],"simulation.":[261]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}