{"id":"https://openalex.org/W1969896938","doi":"https://doi.org/10.1109/tcad.1985.1270127","title":"A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits","display_name":"A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits","publication_year":1985,"publication_date":"1985-07-01","ids":{"openalex":"https://openalex.org/W1969896938","doi":"https://doi.org/10.1109/tcad.1985.1270127","mag":"1969896938"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1985.1270127","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1985.1270127","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5106232660","display_name":"P. Banerjee","orcid":"https://orcid.org/0009-0005-3184-6871"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. Banerjee","raw_affiliation_strings":["Computer Systems Group, Coordinated Science Laboratory, University of Illinois, Urbana-Champaign, Urbana, IL, USA","Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Systems Group, Coordinated Science Laboratory, University of Illinois, Urbana-Champaign, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]},{"raw_affiliation_string":"Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL, USA#TAB#","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068070739","display_name":"Jacob A. Abraham","orcid":"https://orcid.org/0000-0002-5336-5631"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.A. Abraham","raw_affiliation_strings":["Computer Systems Group, Coordinated Science Laboratory, University of Illinois, Urbana-Champaign, Urbana, IL, USA","[Computer Systems Group Coordinated Science Laboratory, University of Illinois, Urbana-Champaign, Urbana, IL, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Systems Group, Coordinated Science Laboratory, University of Illinois, Urbana-Champaign, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]},{"raw_affiliation_string":"[Computer Systems Group Coordinated Science Laboratory, University of Illinois, Urbana-Champaign, Urbana, IL, USA]","institution_ids":["https://openalex.org/I157725225"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I157725225"],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":1.5159,"has_fulltext":false,"cited_by_count":70,"citation_normalized_percentile":{"value":0.7920868,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":"4","issue":"3","first_page":"312","last_page":"321"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.7509371638298035},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.6725417375564575},{"id":"https://openalex.org/keywords/boolean-algebra","display_name":"Boolean algebra","score":0.5935015678405762},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5752818584442139},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5156897306442261},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4868985712528229},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.43279415369033813},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.41866326332092285},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3555980920791626},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2753778100013733},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22323399782180786},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16809913516044617},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.08567848801612854}],"concepts":[{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.7509371638298035},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.6725417375564575},{"id":"https://openalex.org/C39685927","wikidata":"https://www.wikidata.org/wiki/Q173183","display_name":"Boolean algebra","level":2,"score":0.5935015678405762},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5752818584442139},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5156897306442261},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4868985712528229},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.43279415369033813},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.41866326332092285},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3555980920791626},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2753778100013733},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22323399782180786},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16809913516044617},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.08567848801612854},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.1985.1270127","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1985.1270127","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W57564191","https://openalex.org/W109658276","https://openalex.org/W1546202437","https://openalex.org/W1666015432","https://openalex.org/W1775423052","https://openalex.org/W1983253480","https://openalex.org/W1989237088","https://openalex.org/W2000692624","https://openalex.org/W2046817879","https://openalex.org/W2089448146","https://openalex.org/W2582932780","https://openalex.org/W2591502897","https://openalex.org/W2736923891","https://openalex.org/W4236231374","https://openalex.org/W4236999695","https://openalex.org/W4285719527","https://openalex.org/W6602321454","https://openalex.org/W6604472262","https://openalex.org/W6638147768","https://openalex.org/W6741400382"],"related_works":["https://openalex.org/W2730314563","https://openalex.org/W2120538654","https://openalex.org/W2058541779","https://openalex.org/W1632369502","https://openalex.org/W2971786152","https://openalex.org/W2288945810","https://openalex.org/W1980639873","https://openalex.org/W2089754124","https://openalex.org/W3006681749","https://openalex.org/W2809889545"],"abstract_inverted_index":{"This":[0,132],"paper":[1,37],"proposes":[2],"a":[3,43,48,56,61,68,119,130,144,152],"new":[4],"logical":[5],"model":[6,33,110,117,136],"for":[7,122,165],"nMOS":[8],"and":[9,14,70,80,149,163],"CMOS":[10],"circuits.":[11],"Existing":[12],"gate-level":[13],"switch-level":[15],"models":[16],"are":[17,77,103,175],"limited":[18],"in":[19,35,39,169],"their":[20],"ability":[21],"to":[22,105,135],"simulate":[23],"MOS":[24,170],"circuit":[25],"behavior":[26,112],"accurately":[27],"when":[28],"modeling":[29],"physical":[30,140,167],"failures.":[31],"The":[32,53,84,98],"proposed":[34],"this":[36],"is":[38,58,89,161],"the":[40,65,73,93,101,111,137,147,159,173],"form":[41],"of":[42,50,55,67,86,95,100,113,118,129,139,151],"multivalued":[44],"algebra":[45,102,160,174],"defined":[46],"on":[47,158],"set":[49],"node":[51,57,69,87],"states.":[52],"state":[54,107],"represented":[59],"as":[60,143],"pairwhere":[62],"\"a\"":[63],"specifies":[64,72],"condition":[66],"\"b\"":[71],"logic":[74,82,96],"level:":[75],"There":[76],"five":[78,81],"conditions":[79],"levels.":[83],"assignment":[85],"states":[88],"done":[90],"dynamically":[91],"during":[92],"process":[94],"simulation.":[97],"rules":[99],"used":[104],"derive":[106],"tables":[108],"that":[109],"transistors.":[114],"Our":[115],"general":[116],"transistor":[120],"allows":[121],"strong":[123],"interactions":[124],"between":[125,146],"all":[126],"three":[127],"terminals":[128],"transistor.":[131,153],"enables":[133],"us":[134],"effects":[138],"failures":[141,168],"such":[142],"short":[145],"gate":[148],"drain":[150],"A":[154],"simulation":[155],"algorithm":[156],"based":[157],"discussed,":[162],"techniques":[164],"simulating":[166],"circuits":[171],"using":[172],"indicated.":[176]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}