{"id":"https://openalex.org/W2074779099","doi":"https://doi.org/10.1109/tcad.1985.1270124","title":"An Integrated Automated Layout Generation System for DSP Circuits","display_name":"An Integrated Automated Layout Generation System for DSP Circuits","publication_year":1985,"publication_date":"1985-07-01","ids":{"openalex":"https://openalex.org/W2074779099","doi":"https://doi.org/10.1109/tcad.1985.1270124","mag":"2074779099"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1985.1270124","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1985.1270124","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088933304","display_name":"Jan M. Rabaey","orcid":"https://orcid.org/0000-0001-6290-4855"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]},{"id":"https://openalex.org/I99464096","display_name":"KU Leuven","ror":"https://ror.org/05f950310","country_code":"BE","type":"education","lineage":["https://openalex.org/I99464096"]}],"countries":["BE","US"],"is_corresponding":false,"raw_author_name":"J.M. Rabaey","raw_affiliation_strings":["Electronics Research Laboratory, University of California, Berkeley, USA","Katholieke Universiteit Leuven, Leuven, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics Research Laboratory, University of California, Berkeley, USA","institution_ids":["https://openalex.org/I95457486"]},{"raw_affiliation_string":"Katholieke Universiteit Leuven, Leuven, Belgium","institution_ids":["https://openalex.org/I99464096"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056912227","display_name":"S.P. Pope","orcid":null},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.P. Pope","raw_affiliation_strings":["University of California, Berkeley, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Berkeley, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087529266","display_name":"R.W. Brodersen","orcid":null},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R.W. Brodersen","raw_affiliation_strings":["Department of Computer Science, University of California, Berkeley, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of California, Berkeley, USA","institution_ids":["https://openalex.org/I95457486"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":7.5796,"has_fulltext":false,"cited_by_count":65,"citation_normalized_percentile":{"value":0.97672824,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"4","issue":"3","first_page":"285","last_page":"296"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12176","display_name":"Optimization and Packing Problems","score":0.9923999905586243,"subfield":{"id":"https://openalex.org/subfields/2209","display_name":"Industrial and Manufacturing Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11814","display_name":"Advanced Manufacturing and Logistics Optimization","score":0.9915000200271606,"subfield":{"id":"https://openalex.org/subfields/2209","display_name":"Industrial and Manufacturing Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7665485143661499},{"id":"https://openalex.org/keywords/modularity","display_name":"Modularity (biology)","score":0.6504358053207397},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.6373742818832397},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5984405279159546},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5694096088409424},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5297644734382629},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5267940163612366},{"id":"https://openalex.org/keywords/representation","display_name":"Representation (politics)","score":0.47991761565208435},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4718340039253235},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46248775720596313},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.4561658501625061},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4389277696609497},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3874567449092865},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.18208041787147522},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.14038997888565063},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12541162967681885},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.11321473121643066}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7665485143661499},{"id":"https://openalex.org/C2779478453","wikidata":"https://www.wikidata.org/wiki/Q6889748","display_name":"Modularity (biology)","level":2,"score":0.6504358053207397},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.6373742818832397},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5984405279159546},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5694096088409424},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5297644734382629},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5267940163612366},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.47991761565208435},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4718340039253235},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46248775720596313},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.4561658501625061},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4389277696609497},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3874567449092865},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.18208041787147522},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.14038997888565063},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12541162967681885},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.11321473121643066},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0},{"id":"https://openalex.org/C94625758","wikidata":"https://www.wikidata.org/wiki/Q7163","display_name":"Politics","level":2,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.1985.1270124","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1985.1270124","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4399999976158142,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1487560373","https://openalex.org/W1593183029","https://openalex.org/W1987980734","https://openalex.org/W2016356916","https://openalex.org/W2047327642","https://openalex.org/W2157211828","https://openalex.org/W2798372937","https://openalex.org/W3144025793","https://openalex.org/W4235454281","https://openalex.org/W6635425850"],"related_works":["https://openalex.org/W4321442002","https://openalex.org/W2015265939","https://openalex.org/W2284072287","https://openalex.org/W2611067230","https://openalex.org/W4235469518","https://openalex.org/W1494561250","https://openalex.org/W4312121077","https://openalex.org/W3211166530","https://openalex.org/W4318224782","https://openalex.org/W2109350679"],"abstract_inverted_index":{"An":[0],"integrated":[1],"CAD":[2],"system":[3,21],"for":[4,13,126],"the":[5,44,50,81,84,87,127,134,142,158,165],"automated":[6],"design":[7,146,167],"of":[8,29,56,59,80,86,114,118,133,144,160],"digital":[9],"signal-processing":[10,137],"(DSP)":[11],"circuits":[12],"audio":[14],"and":[15,62,83,95,99,130,141],"telecommunication":[16],"applications":[17],"is":[18,33,47,70],"described.":[19],"The":[20,66,116,139],"uses":[22],"as":[23],"unique":[24],"input":[25,46],"a":[26,40,57,73,77,91,93,96,111,119,170],"symbolic":[27,45],"description":[28,75],"algorithm.":[30],"This":[31],"representation":[32],"translated":[34],"into":[35,49,72],"an":[36],"actual":[37],"layout":[38,74,104],"using":[39],"two-step":[41],"process.":[42],"First,":[43],"mapped":[48],"target":[51],"architecture,":[52,88],"which":[53],"consists":[54],"basically":[55],"set":[58],"concurrent":[60],"processors":[61],"dedicated":[63,120],"I/O":[64],"circuitry.":[65],"resulting":[67],"hardware":[68],"configuration":[69],"compiled":[71],"through":[76],"full":[78],"exploitation":[79],"hierarchy":[82],"modularity":[85],"calling":[89],"consecutively":[90],"tiler,":[92],"floorplanner,":[94],"global":[97],"placement":[98],"routing":[100],"tool.":[101],"All":[102],"these":[103,161],"generation":[105],"tools":[106],"are":[107],"able":[108],"to":[109,169],"support":[110],"wide":[112],"range":[113],"technologies.":[115],"provision":[117],"register":[121],"transfer":[122],"level":[123],"simulator":[124],"allows":[125],"efficient":[128],"debugging":[129],"algorithmic":[131],"checking":[132],"real-time":[135],"operating":[136],"algorithms.":[138],"efficiency":[140],"usefulness":[143],"this":[145],"methodology":[147],"has":[148],"been":[149],"demonstrated":[150],"by":[151],"multiple":[152],"examples.":[153],"Experiments":[154],"have":[155],"shown":[156],"that":[157],"use":[159],"techniques":[162],"can":[163],"reduce":[164],"complete":[166],"process":[168],"few":[171],"months.":[172]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}