{"id":"https://openalex.org/W1980561377","doi":"https://doi.org/10.1109/tcad.1985.1270122","title":"Design of Testable CMOS Logic Circuits Under Arbitrary Delays","display_name":"Design of Testable CMOS Logic Circuits Under Arbitrary Delays","publication_year":1985,"publication_date":"1985-07-01","ids":{"openalex":"https://openalex.org/W1980561377","doi":"https://doi.org/10.1109/tcad.1985.1270122","mag":"1980561377"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1985.1270122","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1985.1270122","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086131079","display_name":"Niraj K. Jha","orcid":"https://orcid.org/0000-0002-1539-0369"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"N.K. Jha","raw_affiliation_strings":["Computer Systems Group, Coordinated Science Laboratory, University of Illinois, Urbana, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Systems Group, Coordinated Science Laboratory, University of Illinois, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068070739","display_name":"Jacob A. Abraham","orcid":"https://orcid.org/0000-0002-5336-5631"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.A. Abraham","raw_affiliation_strings":["Computer Systems Group, Coordinated Science Laboratory, University of Illinois, Urbana, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Systems Group, Coordinated Science Laboratory, University of Illinois, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I157725225"],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":4.9908,"has_fulltext":false,"cited_by_count":52,"citation_normalized_percentile":{"value":0.96017699,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":"4","issue":"3","first_page":"264","last_page":"269"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7326796054840088},{"id":"https://openalex.org/keywords/initialization","display_name":"Initialization","score":0.7295282483100891},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.6745545864105225},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6038186550140381},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5372595191001892},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5197791457176208},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5153350234031677},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.49397140741348267},{"id":"https://openalex.org/keywords/test-set","display_name":"Test set","score":0.4909720718860626},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.448293000459671},{"id":"https://openalex.org/keywords/function","display_name":"Function (biology)","score":0.44648998975753784},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4447091221809387},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.35612428188323975},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.32889580726623535},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24018704891204834},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19596153497695923},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.18441295623779297},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1431407630443573},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.05357295274734497}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7326796054840088},{"id":"https://openalex.org/C114466953","wikidata":"https://www.wikidata.org/wiki/Q6034165","display_name":"Initialization","level":2,"score":0.7295282483100891},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.6745545864105225},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6038186550140381},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5372595191001892},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5197791457176208},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5153350234031677},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.49397140741348267},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.4909720718860626},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.448293000459671},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.44648998975753784},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4447091221809387},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35612428188323975},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.32889580726623535},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24018704891204834},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19596153497695923},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.18441295623779297},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1431407630443573},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.05357295274734497},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C78458016","wikidata":"https://www.wikidata.org/wiki/Q840400","display_name":"Evolutionary biology","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.1985.1270122","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1985.1270122","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/16","display_name":"Peace, Justice and strong institutions","score":0.6200000047683716}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W33238586","https://openalex.org/W97180957","https://openalex.org/W1983731190","https://openalex.org/W2046817879","https://openalex.org/W2079723798","https://openalex.org/W2167622257","https://openalex.org/W4206163962","https://openalex.org/W4235228648","https://openalex.org/W4247592337"],"related_works":["https://openalex.org/W2120830976","https://openalex.org/W2134454856","https://openalex.org/W1969142133","https://openalex.org/W2006457427","https://openalex.org/W2141396628","https://openalex.org/W4245485844","https://openalex.org/W2120257283","https://openalex.org/W2137555930","https://openalex.org/W2105463797","https://openalex.org/W2152510207"],"abstract_inverted_index":{"The":[0],"sequential":[1],"behavior":[2],"of":[3,10,53,73],"CMOS":[4,89,101],"logic":[5],"circuits":[6],"in":[7,50,56],"the":[8,36,51,57,71],"presence":[9,52],"stuck-open":[11],"faults":[12],"requires":[13],"that":[14,38],"an":[15,85],"initialization":[16],"input":[17,22],"followed":[18],"by":[19],"a":[20,28,31,65,74,99,112],"test":[21,32,75,114],"be":[23,48,79],"applied":[24],"to":[25,110],"detect":[26],"such":[27],"fault.":[29],"However,":[30],"set":[33,115],"based":[34],"on":[35],"assumption":[37],"delays":[39,55],"through":[40],"all":[41],"gates":[42],"and":[43,67],"interconnections":[44],"are":[45],"zero,":[46],"can":[47],"invalidated":[49,80],"arbitrary":[54,82,117],"circuit.":[58],"In":[59],"this":[60],"paper,":[61],"we":[62],"will":[63,96],"present":[64],"necessary":[66],"sufficient":[68],"condition":[69],"for":[70,84,91,104],"existence":[72],"set,":[76],"which":[77],"cannot":[78],"under":[81,116],"delays,":[83],"AND-OR":[86],"or":[87],"OR-AND":[88],"realization":[90,102],"any":[92,105],"given":[93,106],"function.":[94],"We":[95],"also":[97],"introduce":[98],"Hybrid":[100],"which,":[103],"function,":[107],"is":[108],"guaranteed":[109],"have":[111],"valid":[113],"delays.":[118]},"counts_by_year":[],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}
