{"id":"https://openalex.org/W1998976901","doi":"https://doi.org/10.1109/tcad.1985.1270112","title":"Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits","display_name":"Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits","publication_year":1985,"publication_date":"1985-07-01","ids":{"openalex":"https://openalex.org/W1998976901","doi":"https://doi.org/10.1109/tcad.1985.1270112","mag":"1998976901"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1985.1270112","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1985.1270112","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013238154","display_name":"W. Maly","orcid":null},"institutions":[{"id":"https://openalex.org/I4654613","display_name":"University of Warsaw","ror":"https://ror.org/039bjqg32","country_code":"PL","type":"education","lineage":["https://openalex.org/I4654613"]},{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["PL","US"],"is_corresponding":true,"raw_author_name":"W. Maly","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","Department of Electronic Engineering, Technical University of Warsaw, Warsaw, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Department of Electronic Engineering, Technical University of Warsaw, Warsaw, Poland","institution_ids":["https://openalex.org/I4654613"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5013238154"],"corresponding_institution_ids":["https://openalex.org/I4654613","https://openalex.org/I74973139"],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":5.0531,"has_fulltext":false,"cited_by_count":188,"citation_normalized_percentile":{"value":0.95103654,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"4","issue":"3","first_page":"166","last_page":"177"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11301","display_name":"Advanced Surface Polishing Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.8157424926757812},{"id":"https://openalex.org/keywords/lithography","display_name":"Lithography","score":0.7606745958328247},{"id":"https://openalex.org/keywords/yield","display_name":"Yield (engineering)","score":0.6237737536430359},{"id":"https://openalex.org/keywords/point","display_name":"Point (geometry)","score":0.5495730638504028},{"id":"https://openalex.org/keywords/maximization","display_name":"Maximization","score":0.5437577366828918},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.49636346101760864},{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.4948346018791199},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.48026323318481445},{"id":"https://openalex.org/keywords/cad","display_name":"CAD","score":0.46583905816078186},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44123703241348267},{"id":"https://openalex.org/keywords/photolithography","display_name":"Photolithography","score":0.42278924584388733},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.2807465195655823},{"id":"https://openalex.org/keywords/engineering-drawing","display_name":"Engineering drawing","score":0.2511550188064575},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.24294543266296387},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20405492186546326},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.12167146801948547},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11304742097854614},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.07722160220146179}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8157424926757812},{"id":"https://openalex.org/C204223013","wikidata":"https://www.wikidata.org/wiki/Q133036","display_name":"Lithography","level":2,"score":0.7606745958328247},{"id":"https://openalex.org/C134121241","wikidata":"https://www.wikidata.org/wiki/Q899301","display_name":"Yield (engineering)","level":2,"score":0.6237737536430359},{"id":"https://openalex.org/C28719098","wikidata":"https://www.wikidata.org/wiki/Q44946","display_name":"Point (geometry)","level":2,"score":0.5495730638504028},{"id":"https://openalex.org/C2776330181","wikidata":"https://www.wikidata.org/wiki/Q18358244","display_name":"Maximization","level":2,"score":0.5437577366828918},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.49636346101760864},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.4948346018791199},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.48026323318481445},{"id":"https://openalex.org/C194789388","wikidata":"https://www.wikidata.org/wiki/Q17855283","display_name":"CAD","level":2,"score":0.46583905816078186},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44123703241348267},{"id":"https://openalex.org/C105487726","wikidata":"https://www.wikidata.org/wiki/Q622938","display_name":"Photolithography","level":2,"score":0.42278924584388733},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.2807465195655823},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.2511550188064575},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.24294543266296387},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20405492186546326},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.12167146801948547},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11304742097854614},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.07722160220146179},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C191897082","wikidata":"https://www.wikidata.org/wiki/Q11467","display_name":"Metallurgy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.1985.1270112","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1985.1270112","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1488908698","https://openalex.org/W1967575124","https://openalex.org/W1986941465","https://openalex.org/W2041090186","https://openalex.org/W2046045084","https://openalex.org/W2091696547","https://openalex.org/W2092352221","https://openalex.org/W2104440709","https://openalex.org/W2123076790"],"related_works":["https://openalex.org/W3190396005","https://openalex.org/W2149415078","https://openalex.org/W2625379356","https://openalex.org/W2020522377","https://openalex.org/W1977680521","https://openalex.org/W2532313240","https://openalex.org/W2013138940","https://openalex.org/W2805151322","https://openalex.org/W4243293066","https://openalex.org/W2028425944"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"a":[3],"modeling":[4,53],"technique,":[5],"describing":[6],"IC":[7,34],"manufacturing":[8],"yield":[9,41],"losses":[10],"in":[11],"terms":[12],"of":[13,27,32,38,50],"parameters":[14],"characterizing":[15],"lithography":[16],"related":[17],"point":[18],"defects":[19],"and":[20,36,48],"line":[21],"registration":[22],"errors,":[23],"is":[24],"presented.":[25],"Optimization":[26],"geometrical":[28],"design":[29],"rules,":[30],"evaluation":[31],"VLSI":[33],"artwork,":[35],"maximization":[37],"the":[39,51],"wafer":[40],"are":[42],"discussed":[43],"as":[44],"examples":[45],"illustrating":[46],"applications":[47],"advantages":[49],"proposed":[52],"technique.":[54]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":3}],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}