{"id":"https://openalex.org/W2170972352","doi":"https://doi.org/10.1109/tcad.1984.1270072","title":"A Hierarchical Standard Cell Approach for Custom VLSI Design","display_name":"A Hierarchical Standard Cell Approach for Custom VLSI Design","publication_year":1984,"publication_date":"1984-07-01","ids":{"openalex":"https://openalex.org/W2170972352","doi":"https://doi.org/10.1109/tcad.1984.1270072","mag":"2170972352"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1984.1270072","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1984.1270072","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090087261","display_name":"T. Tokuda","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"T. Tokuda","raw_affiliation_strings":["LSI Research Laboratory, Mitsubishi Electric Corporation Limited, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Research Laboratory, Mitsubishi Electric Corporation Limited, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036978789","display_name":"J. Korematsu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"J. Korematsu","raw_affiliation_strings":["LSI Research Laboratory, Mitsubishi Electric Corporation Limited, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Research Laboratory, Mitsubishi Electric Corporation Limited, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056209928","display_name":"O. Tomisawa","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"O. Tomisawa","raw_affiliation_strings":["LSI Research Laboratory, Mitsubishi Electric Corporation Limited, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Research Laboratory, Mitsubishi Electric Corporation Limited, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029785954","display_name":"S. Asai","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"S. Asai","raw_affiliation_strings":["LSI Research Laboratory, Mitsubishi Electric Corporation Limited, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Research Laboratory, Mitsubishi Electric Corporation Limited, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055909460","display_name":"I. Ohkura","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"I. Ohkura","raw_affiliation_strings":["LSI Research Laboratory, Mitsubishi Electric Corporation Limited, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Research Laboratory, Mitsubishi Electric Corporation Limited, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112045385","display_name":"Tatsuya Enomoto","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Enomoto","raw_affiliation_strings":["LSI Research Laboratory, Mitsubishi Electric Corporation Limited, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Research Laboratory, Mitsubishi Electric Corporation Limited, Japan","institution_ids":["https://openalex.org/I4210133125"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5090087261"],"corresponding_institution_ids":["https://openalex.org/I4210133125"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.23067416,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"3","issue":"3","first_page":"172","last_page":"177"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9930999875068665,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.8423919677734375},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.7319040894508362},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5923241972923279},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4934183657169342},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4919714629650116},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4718972146511078},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44962650537490845},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4411733150482178},{"id":"https://openalex.org/keywords/transistor-count","display_name":"Transistor count","score":0.4238448143005371},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.423819899559021},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4105123281478882},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39638644456863403},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.38141465187072754},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3512478470802307},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3420519530773163},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.29440730810165405},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19189122319221497},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07995301485061646},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07431238889694214}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8423919677734375},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.7319040894508362},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5923241972923279},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4934183657169342},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4919714629650116},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4718972146511078},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44962650537490845},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4411733150482178},{"id":"https://openalex.org/C196320899","wikidata":"https://www.wikidata.org/wiki/Q2623746","display_name":"Transistor count","level":4,"score":0.4238448143005371},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.423819899559021},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4105123281478882},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39638644456863403},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.38141465187072754},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3512478470802307},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3420519530773163},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.29440730810165405},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19189122319221497},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07995301485061646},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07431238889694214},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.1984.1270072","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1984.1270072","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8799999952316284,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2137048602","https://openalex.org/W2157230896","https://openalex.org/W4233445286"],"related_works":["https://openalex.org/W2103645363","https://openalex.org/W2072989701","https://openalex.org/W1738647919","https://openalex.org/W3000179092","https://openalex.org/W2050511294","https://openalex.org/W1986774039","https://openalex.org/W2118321428","https://openalex.org/W2137494283","https://openalex.org/W1965232212","https://openalex.org/W1583771840"],"abstract_inverted_index":{"A":[0],"custom":[1],"VLSI":[2],"design":[3,13,19,23,41],"technique,":[4],"using":[5],"an":[6,69],"integrated":[7],"CAD":[8],"system":[9,14,26],"is":[10],"described.":[11],"The":[12,39,60],"features":[15],"on":[16],"the":[17,55,101],"hierarchical":[18,56],"process":[20],"and":[21,84,107],"layout":[22],"capability":[24],"by":[25],"designers":[27],"(customers).":[28],"As":[29],"for":[30,34],"application,":[31],"high-performance":[32],"LSI's":[33],"16-bit":[35],"CPU":[36],"were":[37,91],"developed.":[38],"LSI":[40,61],"was":[42],"accomplished":[43],"in":[44,68],"a":[45,85],"short":[46],"period":[47],"(three":[48],"months":[49],"with":[50,93],"three":[51],"designers)":[52],"due":[53],"to":[54,100],"standard":[57,104],"cell":[58,105],"approach.":[59,109],"chip":[62],"contains":[63],"about":[64],"20":[65],"K":[66],"transistors":[67],"8.84":[70],"mm":[71,74],"X":[72],"8.88":[73],"die":[75],"area.":[76],"High-speed":[77],"operation":[78],"(machine":[79],"cycle":[80],"=":[81],"200":[82],"ns)":[83],"high":[86],"density":[87],"of":[88],"291":[89],"transistors/mm2":[90],"obtained":[92],"low":[94],"power":[95],"consumption":[96],"(1.2":[97],"W)":[98],"owing":[99],"mixed-MOS":[102],"type":[103],"library":[106],"this":[108]},"counts_by_year":[{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}