{"id":"https://openalex.org/W2163653562","doi":"https://doi.org/10.1109/tcad.1984.1270067","title":"A Network Comparison Algorithm for Layout Verification of Integrated Circuits","display_name":"A Network Comparison Algorithm for Layout Verification of Integrated Circuits","publication_year":1984,"publication_date":"1984-04-01","ids":{"openalex":"https://openalex.org/W2163653562","doi":"https://doi.org/10.1109/tcad.1984.1270067","mag":"2163653562"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1984.1270067","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1984.1270067","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057367287","display_name":"Erich Barke","orcid":"https://orcid.org/0000-0001-5744-2940"},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"E. Barke","raw_affiliation_strings":["Institut Fuer Grundlagen Der Elektrotechnik Und Messtechnik Der Universitaet Hannover, Hanover, Germany"],"affiliations":[{"raw_affiliation_string":"Institut Fuer Grundlagen Der Elektrotechnik Und Messtechnik Der Universitaet Hannover, Hanover, Germany","institution_ids":["https://openalex.org/I114112103"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5057367287"],"corresponding_institution_ids":["https://openalex.org/I114112103"],"apc_list":null,"apc_paid":null,"fwci":4.4671,"has_fulltext":false,"cited_by_count":26,"citation_normalized_percentile":{"value":0.94533929,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"3","issue":"2","first_page":"135","last_page":"141"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12111","display_name":"Industrial Vision Systems and Defect Detection","score":0.9922000169754028,"subfield":{"id":"https://openalex.org/subfields/2209","display_name":"Industrial and Manufacturing Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9617999792098999,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7010980844497681},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6205778121948242},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5866502523422241},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.5769367814064026},{"id":"https://openalex.org/keywords/isomorphism","display_name":"Isomorphism (crystallography)","score":0.5011482238769531},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.4356878995895386},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4274345338344574},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.39695656299591064},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.177899569272995},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14533081650733948},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.07514214515686035}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7010980844497681},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6205778121948242},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5866502523422241},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.5769367814064026},{"id":"https://openalex.org/C203436722","wikidata":"https://www.wikidata.org/wiki/Q902950","display_name":"Isomorphism (crystallography)","level":3,"score":0.5011482238769531},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.4356878995895386},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4274345338344574},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.39695656299591064},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.177899569272995},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14533081650733948},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.07514214515686035},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C115624301","wikidata":"https://www.wikidata.org/wiki/Q895901","display_name":"Crystal structure","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C8010536","wikidata":"https://www.wikidata.org/wiki/Q160398","display_name":"Crystallography","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.1984.1270067","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1984.1270067","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W2004890605","https://openalex.org/W2027154999","https://openalex.org/W2095052098","https://openalex.org/W2113145605","https://openalex.org/W2151684844","https://openalex.org/W2154878346","https://openalex.org/W2168023416","https://openalex.org/W2171467631","https://openalex.org/W3214091992","https://openalex.org/W4232329767","https://openalex.org/W4248604433","https://openalex.org/W6651723346","https://openalex.org/W6682576761","https://openalex.org/W6803679366"],"related_works":["https://openalex.org/W2086397253","https://openalex.org/W2133122801","https://openalex.org/W600422426","https://openalex.org/W4288024920","https://openalex.org/W2987986312","https://openalex.org/W2007156430","https://openalex.org/W2170882281","https://openalex.org/W3215142653","https://openalex.org/W1487051936","https://openalex.org/W194748710"],"abstract_inverted_index":{"An":[0],"algorithm":[1],"is":[2,57],"presented":[3],"which":[4],"compares":[5],"the":[6,22,27,50,53,60],"actual":[7],"topology":[8],"of":[9,21,52,62,101],"an":[10,74,98],"integrated":[11],"circuit":[12,25],"derived":[13],"from":[14],"its":[15],"layout":[16,78],"with":[17],"a":[18,102],"user-supplied":[19],"description":[20],"intended":[23],"nominal":[24],"at":[26],"transistor":[28],"level.":[29],"Devices":[30],"and":[31,45,59,64,71],"nets":[32,65],"in":[33,73],"both":[34],"circuits":[35],"may":[36],"be":[37,89],"named":[38],"arbitrarily.":[39],"Using":[40],"information":[41],"about":[42],"device":[43],"types":[44,47],"pin":[46],"to":[48,88],"weight":[49],"nodes":[51],"corresponding":[54],"graphs,":[55],"isomorphism":[56],"tested":[58],"names":[61],"devices":[63],"are":[66,69],"matched.":[67],"Differences":[68],"isolated":[70],"result":[72],"error":[75],"report":[76],"for":[77,92],"correction.":[79],"The":[80],"implemented":[81],"program":[82],"NEtwork":[83],"COMparison":[84],"(NECOM)":[85],"has":[86],"proven":[87],"particularly":[90],"efficient":[91],"analog":[93],"bipolar":[94],"circuits.":[95],"It":[96],"represents":[97],"essential":[99],"part":[100],"recently":[103],"developed":[104],"complete":[105],"mask":[106],"artwork":[107],"analysis":[108],"system":[109],"called":[110],"ALAS.":[111]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}