{"id":"https://openalex.org/W2168380797","doi":"https://doi.org/10.1109/tcad.1983.1270048","title":"Routing Techniques for Gate Array","display_name":"Routing Techniques for Gate Array","publication_year":1983,"publication_date":"1983-10-01","ids":{"openalex":"https://openalex.org/W2168380797","doi":"https://doi.org/10.1109/tcad.1983.1270048","mag":"2168380797"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1983.1270048","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1983.1270048","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067952078","display_name":"B. Ting","orcid":null},"institutions":[{"id":"https://openalex.org/I200576644","display_name":"HRL Laboratories (United States)","ror":"https://ror.org/05p7te762","country_code":"US","type":"company","lineage":["https://openalex.org/I200576644"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B.S. Ting","raw_affiliation_strings":["Hughes Aircraft Company, Newport Beach, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Hughes Aircraft Company, Newport Beach, CA, USA","institution_ids":["https://openalex.org/I200576644"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023005854","display_name":"B. N. Tien","orcid":null},"institutions":[{"id":"https://openalex.org/I200576644","display_name":"HRL Laboratories (United States)","ror":"https://ror.org/05p7te762","country_code":"US","type":"company","lineage":["https://openalex.org/I200576644"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bou Nin Tien","raw_affiliation_strings":["Hughes Aircraft Company, Newport Beach, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Hughes Aircraft Company, Newport Beach, CA, USA","institution_ids":["https://openalex.org/I200576644"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I200576644"],"apc_list":null,"apc_paid":null,"fwci":5.1695,"has_fulltext":false,"cited_by_count":86,"citation_normalized_percentile":{"value":0.9560333,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"2","issue":"4","first_page":"301","last_page":"312"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6733232140541077},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5991888046264648},{"id":"https://openalex.org/keywords/multipath-routing","display_name":"Multipath routing","score":0.5245511531829834},{"id":"https://openalex.org/keywords/static-routing","display_name":"Static routing","score":0.5029489398002625},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4816633462905884},{"id":"https://openalex.org/keywords/hierarchical-routing","display_name":"Hierarchical routing","score":0.45358896255493164},{"id":"https://openalex.org/keywords/link-state-routing-protocol","display_name":"Link-state routing protocol","score":0.4399360418319702},{"id":"https://openalex.org/keywords/equal-cost-multi-path-routing","display_name":"Equal-cost multi-path routing","score":0.41687384247779846},{"id":"https://openalex.org/keywords/policy-based-routing","display_name":"Policy-based routing","score":0.41348686814308167},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.338795006275177},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33444744348526},{"id":"https://openalex.org/keywords/routing-protocol","display_name":"Routing protocol","score":0.2802474796772003},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2592470347881317}],"concepts":[{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6733232140541077},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5991888046264648},{"id":"https://openalex.org/C76522221","wikidata":"https://www.wikidata.org/wiki/Q5035396","display_name":"Multipath routing","level":5,"score":0.5245511531829834},{"id":"https://openalex.org/C204948658","wikidata":"https://www.wikidata.org/wiki/Q1119410","display_name":"Static routing","level":4,"score":0.5029489398002625},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4816633462905884},{"id":"https://openalex.org/C177818476","wikidata":"https://www.wikidata.org/wiki/Q12878103","display_name":"Hierarchical routing","level":5,"score":0.45358896255493164},{"id":"https://openalex.org/C89305328","wikidata":"https://www.wikidata.org/wiki/Q1755411","display_name":"Link-state routing protocol","level":4,"score":0.4399360418319702},{"id":"https://openalex.org/C115443555","wikidata":"https://www.wikidata.org/wiki/Q5367790","display_name":"Equal-cost multi-path routing","level":5,"score":0.41687384247779846},{"id":"https://openalex.org/C196423136","wikidata":"https://www.wikidata.org/wiki/Q7209671","display_name":"Policy-based routing","level":5,"score":0.41348686814308167},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.338795006275177},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33444744348526},{"id":"https://openalex.org/C104954878","wikidata":"https://www.wikidata.org/wiki/Q1648707","display_name":"Routing protocol","level":3,"score":0.2802474796772003},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2592470347881317}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.1983.1270048","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1983.1270048","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.44999998807907104,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1975675300","https://openalex.org/W1980129108","https://openalex.org/W1985694994","https://openalex.org/W1987980734","https://openalex.org/W1991530123","https://openalex.org/W2011039300","https://openalex.org/W2036265926","https://openalex.org/W2037020301","https://openalex.org/W2060632898","https://openalex.org/W2062399354","https://openalex.org/W2064086982","https://openalex.org/W2066356146","https://openalex.org/W2071116455","https://openalex.org/W2097774291","https://openalex.org/W2120542406","https://openalex.org/W2127980272","https://openalex.org/W2141461755","https://openalex.org/W2151511941","https://openalex.org/W2153580689","https://openalex.org/W2161014683","https://openalex.org/W2163929525","https://openalex.org/W2293339222","https://openalex.org/W3138807513","https://openalex.org/W4234660537","https://openalex.org/W4242836539","https://openalex.org/W4251316929","https://openalex.org/W6646755501","https://openalex.org/W6666030435","https://openalex.org/W6678626478"],"related_works":["https://openalex.org/W2181601090","https://openalex.org/W4253436398","https://openalex.org/W2068473861","https://openalex.org/W2607223747","https://openalex.org/W2351878639","https://openalex.org/W2556128816","https://openalex.org/W2369989480","https://openalex.org/W3046124320","https://openalex.org/W4211082391","https://openalex.org/W2149643156"],"abstract_inverted_index":{"This":[0,19],"paper":[1,56],"describes":[2],"the":[3,50,59,76,130,133],"routing":[4,40,65,77,104,122],"techniques":[5,87],"used":[6],"for":[7],"a":[8,35,72,94],"Hughes":[9],"internally":[10],"developed":[11],"high-density":[12],"silicon-gate":[13],"bulk":[14],"CMOS":[15],"gate":[16],"array":[17,28],"family.":[18],"layout":[20],"software":[21],"can":[22],"be":[23],"easily":[24],"adapted":[25],"to":[26,48,92,116,128],"different":[27],"sizes":[29],"and/or":[30],"technologies":[31],"(e.g.,":[32],"bipolar)":[33],"through":[34],"change":[36],"of":[37,63,75,83,97,132],"parameters.":[38],"A":[39],"model":[41],"and":[42,61,66,70,88,112],"hierarchical":[43],"decomposition":[44],"schemes":[45],"are":[46,90,108,114,126],"presented":[47],"address":[49],"routability":[51],"issue.":[52],"More":[53],"specifically,":[54],"this":[55],"focuses":[57],"on":[58],"formulation":[60],"analysis":[62],"global":[64],"vertical":[67],"assignment":[68],"problems":[69],"gives":[71],"systematic":[73],"breakdown":[74],"task":[78],"into":[79],"well-defined":[80],"subtasks.":[81,102],"Instead":[82],"performing":[84],"sequential":[85],"routing,":[86],"formulations":[89],"introduced":[91],"achieve":[93],"high":[95],"degree":[96],"order":[98,118],"independency":[99],"in":[100,120],"all":[101],"In":[103],"subtasks":[105],"where":[106],"iterations":[107],"required,":[109],"independent":[110],"selection":[111],"interconnection":[113],"performed":[115],"avoid":[117],"dependency":[119],"typical":[121],"problems.":[123],"Implementation":[124],"results":[125],"provided":[127],"indicate":[129],"efficiency":[131],"system.":[134]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}