{"id":"https://openalex.org/W2157230896","doi":"https://doi.org/10.1109/tcad.1983.1270030","title":"Delay-Time Modeling for ED MOS Logic LSI","display_name":"Delay-Time Modeling for ED MOS Logic LSI","publication_year":1983,"publication_date":"1983-07-01","ids":{"openalex":"https://openalex.org/W2157230896","doi":"https://doi.org/10.1109/tcad.1983.1270030","mag":"2157230896"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.1983.1270030","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1983.1270030","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090087261","display_name":"T. Tokuda","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"T. Tokuda","raw_affiliation_strings":["LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033444591","display_name":"Kaoru Okazaki","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Okazaki","raw_affiliation_strings":["LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045455684","display_name":"K. Sakashita","orcid":"https://orcid.org/0000-0003-2602-7837"},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Sakashita","raw_affiliation_strings":["LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055909460","display_name":"I. Ohkura","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"I. Ohkura","raw_affiliation_strings":["LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112045385","display_name":"Tatsuya Enomoto","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Enomoto","raw_affiliation_strings":["LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5090087261"],"corresponding_institution_ids":["https://openalex.org/I4210133125"],"apc_list":null,"apc_paid":null,"fwci":5.7134,"has_fulltext":false,"cited_by_count":34,"citation_normalized_percentile":{"value":0.96297651,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":"2","issue":"3","first_page":"129","last_page":"134"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9911999702453613,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9891999959945679,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.8782138824462891},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.7377586364746094},{"id":"https://openalex.org/keywords/transmission-gate","display_name":"Transmission gate","score":0.6470998525619507},{"id":"https://openalex.org/keywords/waveform","display_name":"Waveform","score":0.6030712723731995},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.573340892791748},{"id":"https://openalex.org/keywords/transmission-delay","display_name":"Transmission delay","score":0.5671730637550354},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5611419677734375},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5410401225090027},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.5102026462554932},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.4978299140930176},{"id":"https://openalex.org/keywords/and-gate","display_name":"AND gate","score":0.4525914490222931},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4393068552017212},{"id":"https://openalex.org/keywords/transmission","display_name":"Transmission (telecommunications)","score":0.4339224398136139},{"id":"https://openalex.org/keywords/group-delay-and-phase-delay","display_name":"Group delay and phase delay","score":0.41058388352394104},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.28561145067214966},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27337411046028137},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.21575164794921875},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2062297761440277},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.18093764781951904},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.15978196263313293},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.13789474964141846},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.11641332507133484},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08965045213699341}],"concepts":[{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.8782138824462891},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.7377586364746094},{"id":"https://openalex.org/C2780949067","wikidata":"https://www.wikidata.org/wiki/Q1136752","display_name":"Transmission gate","level":4,"score":0.6470998525619507},{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.6030712723731995},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.573340892791748},{"id":"https://openalex.org/C108921912","wikidata":"https://www.wikidata.org/wiki/Q7834639","display_name":"Transmission delay","level":3,"score":0.5671730637550354},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5611419677734375},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5410401225090027},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.5102026462554932},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4978299140930176},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.4525914490222931},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4393068552017212},{"id":"https://openalex.org/C761482","wikidata":"https://www.wikidata.org/wiki/Q118093","display_name":"Transmission (telecommunications)","level":2,"score":0.4339224398136139},{"id":"https://openalex.org/C123792056","wikidata":"https://www.wikidata.org/wiki/Q365988","display_name":"Group delay and phase delay","level":3,"score":0.41058388352394104},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.28561145067214966},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27337411046028137},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.21575164794921875},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2062297761440277},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.18093764781951904},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.15978196263313293},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.13789474964141846},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.11641332507133484},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08965045213699341},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.1983.1270030","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.1983.1270030","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5600000023841858,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2097435374","https://openalex.org/W2137048602","https://openalex.org/W2139086898"],"related_works":["https://openalex.org/W2157230896","https://openalex.org/W2121192822","https://openalex.org/W2384364837","https://openalex.org/W3133026170","https://openalex.org/W2034398607","https://openalex.org/W3145888793","https://openalex.org/W2908954988","https://openalex.org/W2087468076","https://openalex.org/W4302376515","https://openalex.org/W2139145693"],"abstract_inverted_index":{"The":[0,46,103,114,176],"propagation":[1,104],"delay":[2,29,49,73,81,88,105,148,152,183],"time":[3,30,50,194,212],"of":[4,37,41,61,71,99,107,116,147,154,213],"the":[5,26,38,43,55,62,68,72,87,96,100,108,117,134,137,141,182,208],"ED":[6],"MOS":[7],"logic":[8,77,101,163,171,197,215],"gate":[9,44,63,110,119,143,156],"is":[10,32,52,83,185,205],"precisely":[11,112],"analyzed":[12],"considering":[13,86],"input":[14,56,93],"waveform":[15],"and":[16,23,58,127,140,192],"loading":[17],"conditions.":[18],"According":[19],"to":[20,91,131,189],"theoretical":[21],"consideration":[22],"circuit":[24,202],"analysis,":[25],"rise":[27],"mode":[28,48,126],"tpLH":[31],"approximated":[33],"as":[34,165],"a":[35,76,170,196,214],"function":[36],"output":[39,59,97],"capacitance":[40,57,60],"only":[42],"concerned.":[45,64],"fall":[47],"t.pHL":[51],"determined":[53],"by":[54,85],"These":[65],"results":[66],"allow":[67],"easy":[69],"implementation":[70],"model":[74,184],"into":[75,122],"simulator.":[78,216],"A":[79],"precise":[80],"simulation":[82],"attained":[84],"components,":[89],"corresponding":[90],"each":[92,132,155],"node,":[94],"at":[95],"side":[98],"element.":[102],"times":[106,153],"transmission":[109,118,135],"are":[111,120],"analyzed.":[113],"operations":[115],"divided":[121],"two":[123,145],"modes;":[124],"synchronous":[125],"asynchronous":[128],"mode.":[129],"Corresponding":[130],"mode,":[133],"gate,":[136,139],"preceding":[138],"succeeding":[142],"have":[144,173],"kinds":[146],"times.":[149],"To":[150],"simulate":[151],"precisely,":[157],"models":[158],"which":[159],"treat":[160],"these":[161],"three":[162],"elements":[164],"one":[166],"primitive":[167],"element":[168],"in":[169,195,207],"simulator":[172,203],"been":[174],"proposed.":[175],"new":[177],"timing":[178],"verification":[179],"method":[180],"using":[181],"evaluated":[186],"with":[187],"respect":[188],"delay-time":[190],"accuracy":[191,204],"execusion":[193],"LSI.":[198],"Through":[199],"this":[200],"method,":[201],"obtained":[206],"short":[209],"computer":[210],"run":[211]},"counts_by_year":[],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}