{"id":"https://openalex.org/W4391827236","doi":"https://doi.org/10.1109/tc.2024.3365954","title":"Efficient Deadlock Avoidance for 2-D Mesh NoCs That Use OQ or VOQ Routers","display_name":"Efficient Deadlock Avoidance for 2-D Mesh NoCs That Use OQ or VOQ Routers","publication_year":2024,"publication_date":"2024-02-14","ids":{"openalex":"https://openalex.org/W4391827236","doi":"https://doi.org/10.1109/tc.2024.3365954"},"language":"en","primary_location":{"id":"doi:10.1109/tc.2024.3365954","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2024.3365954","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014027604","display_name":"Philippos Papaphilippou","orcid":"https://orcid.org/0000-0002-7452-7150"},"institutions":[{"id":"https://openalex.org/I205274468","display_name":"Trinity College Dublin","ror":"https://ror.org/02tyrky19","country_code":"IE","type":"education","lineage":["https://openalex.org/I205274468"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Philippos Papaphilippou","raw_affiliation_strings":["School of Computer Science &#x0026; Statistics, Trinity College Dublin, Dublin, Ireland"],"raw_orcid":"https://orcid.org/0000-0002-7452-7150","affiliations":[{"raw_affiliation_string":"School of Computer Science &#x0026; Statistics, Trinity College Dublin, Dublin, Ireland","institution_ids":["https://openalex.org/I205274468"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026757519","display_name":"Thiem Van Chu","orcid":"https://orcid.org/0000-0002-2003-2574"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Thiem Van Chu","raw_affiliation_strings":["Tokyo Institute of Technology, Yokohama, Kanagawa, Japan"],"raw_orcid":"https://orcid.org/0000-0002-2003-2574","affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Yokohama, Kanagawa, Japan","institution_ids":["https://openalex.org/I114531698"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2495,"currency":"USD","value_usd":2495},"apc_paid":null,"fwci":2.4182,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.88443677,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"73","issue":"5","first_page":"1414","last_page":"1426"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10179","display_name":"Supercapacitor Materials and Fabrication","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/2504","display_name":"Electronic, Optical and Magnetic Materials"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9904000163078308,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8186919689178467},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.6014854311943054},{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.5518638491630554},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.546217679977417},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.518219530582428},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.4916394352912903},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.4658283591270447},{"id":"https://openalex.org/keywords/deadlock-prevention-algorithms","display_name":"Deadlock prevention algorithms","score":0.4568134546279907},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.44950780272483826},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.4128551483154297}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8186919689178467},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.6014854311943054},{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.5518638491630554},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.546217679977417},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.518219530582428},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.4916394352912903},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.4658283591270447},{"id":"https://openalex.org/C113429609","wikidata":"https://www.wikidata.org/wiki/Q4060699","display_name":"Deadlock prevention algorithms","level":3,"score":0.4568134546279907},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.44950780272483826},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4128551483154297},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.2024.3365954","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2024.3365954","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"display_name":"Peace, Justice and strong institutions","id":"https://metadata.un.org/sdg/16"}],"awards":[{"id":"https://openalex.org/G5622264776","display_name":"In-Storage Accelerator Architectures for Large-Scale Sparse Matrix Processing","funder_award_id":"21K17720","funder_id":"https://openalex.org/F4320334764","funder_display_name":"Japan Society for the Promotion of Science"}],"funders":[{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W35708471","https://openalex.org/W1501077214","https://openalex.org/W1644436786","https://openalex.org/W1958215124","https://openalex.org/W1969449685","https://openalex.org/W1994115018","https://openalex.org/W2003860501","https://openalex.org/W2008041840","https://openalex.org/W2044206819","https://openalex.org/W2095795217","https://openalex.org/W2097027683","https://openalex.org/W2119476394","https://openalex.org/W2124552466","https://openalex.org/W2142127152","https://openalex.org/W2155765360","https://openalex.org/W2170116489","https://openalex.org/W2231036065","https://openalex.org/W2540538829","https://openalex.org/W2884810594","https://openalex.org/W2891991377","https://openalex.org/W2978727842","https://openalex.org/W3141710531","https://openalex.org/W3157297576","https://openalex.org/W3217443110","https://openalex.org/W4240506049","https://openalex.org/W4245160202","https://openalex.org/W4280494913","https://openalex.org/W4312942943","https://openalex.org/W4321608261","https://openalex.org/W7055345005"],"related_works":["https://openalex.org/W2050076411","https://openalex.org/W1542183432","https://openalex.org/W2001478969","https://openalex.org/W2360686363","https://openalex.org/W1900787600","https://openalex.org/W2136552483","https://openalex.org/W2117224408","https://openalex.org/W2166954426","https://openalex.org/W3137070212","https://openalex.org/W2379911191"],"abstract_inverted_index":{"Network-on-chips":[0],"(NoCs)":[1],"are":[2,61],"currently":[3],"a":[4,32,51,88,96,134,150,178],"widely":[5],"used":[6],"approach":[7,161],"for":[8,18,35,99,138],"achieving":[9],"scalability":[10],"of":[11,70,85,95,120,202],"multi-cores":[12],"to":[13,56,187],"many-cores,":[14],"as":[15,17,41,43,107,109,124,177],"well":[16,42,108],"interconnecting":[19],"other":[20],"vital":[21],"system-on-chip":[22],"(SoC)":[23],"components.":[24],"Each":[25],"entity":[26,45],"in":[27],"2D":[28],"mesh-based":[29],"NoCs":[30],"has":[31],"router":[33],"responsible":[34],"forwarding":[36],"packets":[37],"between":[38,64],"the":[39,44,57,68,79,93,118,188,192,200],"dimensions":[40],"itself,":[46],"and":[47,67,169,191],"it":[48],"is":[49,195],"essentially":[50],"5-port":[52],"switch.":[53],"With":[54],"respect":[55],"routing":[58,65,175],"algorithm,":[59],"there":[60],"important":[62],"trade-offs":[63],"performance":[66,201],"efficiency":[69],"overcoming":[71],"potential":[72],"deadlocks.":[73],"Common":[74],"deadlock":[75,104,135,207],"avoidance":[76,111,136],"techniques":[77],"including":[78],"turn":[80],"model":[81],"usually":[82],"involve":[83],"restrictions":[84,165],"certain":[86],"paths":[87],"packet":[89],"can":[90,170],"take":[91],"at":[92,117],"cost":[94],"higher":[97],"probability":[98],"network":[100],"congestion.":[101],"In":[102],"contrast,":[103],"resolution":[105],"techniques,":[106,168],"some":[110],"schemes,":[112],"provide":[113],"more":[114],"path":[115,164],"flexibility":[116],"expense":[119],"hardware":[121],"complexity,":[122],"such":[123],"by":[125],"incorporating":[126],"(or":[127],"assuming)":[128],"dedicated":[129],"buffers.":[130],"This":[131,183],"paper":[132],"provides":[133],"algorithm":[137,198],"NoC":[139],"routers":[140],"based":[141,172],"on":[142,152,155,173],"output-queues":[143],"(OQs)":[144],"or":[145,181],"virtual-output":[146],"queues":[147],"(VOQs),":[148],"with":[149],"focus":[151],"their":[153],"use":[154],"field-programmable":[156],"gate-arrays":[157],"(FPGAs).":[158],"The":[159],"proposed":[160],"features":[162],"fewer":[163],"than":[166],"common":[167],"be":[171],"existing":[174],"algorithms":[176],"baseline,":[179],"deadlock-free":[180],"not.":[182],"requires":[184],"no":[185],"modification":[186],"queueing":[189],"topology,":[190],"required":[193],"logic":[194],"minimal.":[196],"Our":[197],"approaches":[199],"fully-adaptive":[203],"algorithms,":[204],"while":[205],"maintaining":[206],"freedom.":[208]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":8},{"year":2024,"cited_by_count":1}],"updated_date":"2026-08-28T12:50:07.497085","created_date":"2025-10-10T00:00:00"}
