{"id":"https://openalex.org/W4391249356","doi":"https://doi.org/10.1109/tc.2024.3355779","title":"Achieving DRAM-Like PCM by Trading Off Capacity for Latency","display_name":"Achieving DRAM-Like PCM by Trading Off Capacity for Latency","publication_year":2024,"publication_date":"2024-01-26","ids":{"openalex":"https://openalex.org/W4391249356","doi":"https://doi.org/10.1109/tc.2024.3355779"},"language":"en","primary_location":{"id":"doi:10.1109/tc.2024.3355779","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2024.3355779","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061065618","display_name":"Irina Alam","orcid":"https://orcid.org/0000-0002-7927-8405"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Irina Alam","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California, Los Angeles, CA, USA"],"raw_orcid":"https://orcid.org/0000-0002-7927-8405","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084229134","display_name":"Puneet Gupta","orcid":"https://orcid.org/0000-0002-6188-1134"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Puneet Gupta","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California, Los Angeles, CA, USA"],"raw_orcid":"https://orcid.org/0000-0002-6188-1134","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I161318765"],"apc_list":{"value":2495,"currency":"USD","value_usd":2495},"apc_paid":null,"fwci":1.5627,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.81576145,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":93,"max":98},"biblio":{"volume":"73","issue":"4","first_page":"1180","last_page":"1189"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11315","display_name":"Phase-change materials and chalcogenides","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/2505","display_name":"Materials Chemistry"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.9100558161735535},{"id":"https://openalex.org/keywords/phase-change-memory","display_name":"Phase-change memory","score":0.7086721062660217},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.6690008640289307},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6664378643035889},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6181255578994751},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5848740339279175},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5740413069725037},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.48843398690223694},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.4762294888496399},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4536416828632355},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4237896203994751},{"id":"https://openalex.org/keywords/row","display_name":"Row","score":0.42233991622924805},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.3353468179702759},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.32069891691207886},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.30729731917381287},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.28301888704299927},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.23187774419784546},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17034175992012024},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10242432355880737},{"id":"https://openalex.org/keywords/phase-change","display_name":"Phase change","score":0.08396443724632263},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.07965943217277527}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.9100558161735535},{"id":"https://openalex.org/C64142963","wikidata":"https://www.wikidata.org/wiki/Q1153902","display_name":"Phase-change memory","level":3,"score":0.7086721062660217},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.6690008640289307},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6664378643035889},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6181255578994751},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5848740339279175},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5740413069725037},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.48843398690223694},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.4762294888496399},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4536416828632355},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4237896203994751},{"id":"https://openalex.org/C135598885","wikidata":"https://www.wikidata.org/wiki/Q1366302","display_name":"Row","level":2,"score":0.42233991622924805},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.3353468179702759},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.32069891691207886},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.30729731917381287},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.28301888704299927},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.23187774419784546},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17034175992012024},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10242432355880737},{"id":"https://openalex.org/C133256868","wikidata":"https://www.wikidata.org/wiki/Q7180940","display_name":"Phase change","level":2,"score":0.08396443724632263},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.07965943217277527},{"id":"https://openalex.org/C61696701","wikidata":"https://www.wikidata.org/wiki/Q770766","display_name":"Engineering physics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.2024.3355779","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2024.3355779","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W35708471","https://openalex.org/W109781734","https://openalex.org/W1983826793","https://openalex.org/W2010795939","https://openalex.org/W2036934942","https://openalex.org/W2039631162","https://openalex.org/W2047644389","https://openalex.org/W2063799733","https://openalex.org/W2083383375","https://openalex.org/W2084486220","https://openalex.org/W2102449048","https://openalex.org/W2103498248","https://openalex.org/W2111104031","https://openalex.org/W2147657366","https://openalex.org/W2155462575","https://openalex.org/W2930731691","https://openalex.org/W2985656529","https://openalex.org/W2986309553","https://openalex.org/W2986766728","https://openalex.org/W3042624570","https://openalex.org/W4240175258","https://openalex.org/W4244361616","https://openalex.org/W6642343278"],"related_works":["https://openalex.org/W3008068282","https://openalex.org/W2185658074","https://openalex.org/W2896161911","https://openalex.org/W4285245242","https://openalex.org/W2907559171","https://openalex.org/W4243618206","https://openalex.org/W2019238062","https://openalex.org/W2138825797","https://openalex.org/W4393076761","https://openalex.org/W1725472669"],"abstract_inverted_index":{"Phase":[0],"Change":[1],"Memory":[2],"(PCM)":[3],"is":[4],"considered":[5],"one":[6],"of":[7],"the":[8,69,73,111,122,130,139,145,157,197,210,236],"most":[9],"promising":[10],"scalable":[11],"non-volatile":[12],"main":[13,30,187,206,221,227,238],"memory":[14,31,54,75,119,188,207,222,228,239],"alternatives":[15],"to":[16,42,78,101,153,195],"DRAM.":[17],"It":[18],"provides$\\sim$4x-5x":[19],"cost":[20],"per":[21],"bit":[22],"advantage":[23],"over":[24,162],"DRAM,":[25,39],"thus":[26],"enabling":[27],"cost-effective":[28],"dense":[29],"solution.":[32],"However,":[33],"PCM":[34,63,84,94,103,112,135,159,212],"accesses":[35],"are":[36,124],"slower":[37,211],"than":[38,171],"which":[40],"leads":[41],"significantly":[43],"poorer":[44],"overall":[45,146,158],"system":[46,216],"performance":[47,70],"(upto":[48],"80%":[49],"higher":[50],"execution":[51],"time":[52,141],"for":[53,209],"intensive":[55],"applications":[56],"based":[57,229],"on":[58],"our":[59],"analysis).":[60],"To":[61],"use":[62],"as":[64,184],"a":[65,115,128],"viable":[66],"DRAM":[67,163,172,186,233],"replacement,":[68],"gap":[71],"between":[72],"two":[74,134],"technologies":[76],"has":[77,114],"be":[79,182,193],"bridged,":[80],"primarily":[81],"by":[82,231],"improving":[83],"read":[85,104,177],"latency.":[86,105,178],"In":[87,106],"this":[88],"work":[89],"we":[90],"propose":[91],"an":[92],"optimized":[93],"architecture,":[95],"PCM-Duplicate,":[96,107],"that":[97],"trades":[98],"off":[99],"capacity":[100,170,223],"improve":[102,220],"every":[108],"row":[109],"in":[110,203],"subarray":[113],"duplicate":[116],"row.":[117],"During":[118],"read,":[120],"both":[121],"rows":[123],"activated":[125],"simultaneously.":[126],"As":[127],"result,":[129],"bitline":[131],"discharges":[132],"through":[133],"cells.":[136],"This":[137],"reduces":[138],"discharge":[140],"significantly,":[142],"bringing":[143],"down":[144],"sensing":[147],"latency":[148],"by$":[149],"\\gt":[150],"$3x":[151],"compared":[152],"baseline":[154],"PCM.":[155],"While":[156],"density":[160],"benefit":[161],"halves,":[164],"it":[165,191],"still":[166],"provides":[167],"2x":[168],"more":[169],"while":[173],"having":[174],"almost":[175],"comparable":[176],"PCM-Duplicate":[179],"can":[180,192],"either":[181],"used":[183,194,202],"low-cost":[185],"alternative":[189],"or":[190],"replace":[196],"DRAM-based":[198],"last":[199],"level":[200],"cache":[201],"today's":[204],"hybrid":[205],"systems":[208],"memories.":[213],"Both":[214],"these":[215],"options":[217],"not":[218],"only":[219],"but":[224],"also":[225],"allow":[226],"persistence":[230],"replacing":[232],"and":[234],"making":[235],"entire":[237],"non-volatile.":[240]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":4}],"updated_date":"2026-08-28T12:50:07.497085","created_date":"2025-10-10T00:00:00"}
