{"id":"https://openalex.org/W3217082322","doi":"https://doi.org/10.1109/tc.2021.3117316","title":"Guest Editorial: IEEE TC Special Section on Compiler Optimizations for FPGA-Based Systems","display_name":"Guest Editorial: IEEE TC Special Section on Compiler Optimizations for FPGA-Based Systems","publication_year":2021,"publication_date":"2021-12-01","ids":{"openalex":"https://openalex.org/W3217082322","doi":"https://doi.org/10.1109/tc.2021.3117316","mag":"3217082322"},"language":"en","primary_location":{"id":"mag:3217082322","is_oa":false,"landing_page_url":"https://dblp.uni-trier.de/db/journals/tc/tc70.html#CardosoDP21","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Computers","raw_type":null},"type":"editorial","indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007667456","display_name":"Jo\u00e3o M. P. Cardoso","orcid":"https://orcid.org/0000-0002-7353-1799"},"institutions":[{"id":"https://openalex.org/I182534213","display_name":"Universidade do Porto","ror":"https://ror.org/043pwc612","country_code":"PT","type":"education","lineage":["https://openalex.org/I182534213"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Jo\u00e3o M. P. Cardoso","raw_affiliation_strings":["Department of Informatics Engineering Faculty of Engineering, University of Porto Porto, Portugal"],"raw_orcid":"https://orcid.org/0000-0002-7353-1799","affiliations":[{"raw_affiliation_string":"Department of Informatics Engineering Faculty of Engineering, University of Porto Porto, Portugal","institution_ids":["https://openalex.org/I182534213"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087585086","display_name":"Andr\u00e9 DeHon","orcid":"https://orcid.org/0000-0001-9177-7699"},"institutions":[{"id":"https://openalex.org/I79576946","display_name":"University of Pennsylvania","ror":"https://ror.org/00b30xv10","country_code":"US","type":"education","lineage":["https://openalex.org/I79576946"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andr\u00e9 DeHon","raw_affiliation_strings":["Electrical and Systems Engineering Department, University of Pennsylvania, Philadelphia, PA, USA"],"raw_orcid":"https://orcid.org/0000-0001-9177-7699","affiliations":[{"raw_affiliation_string":"Electrical and Systems Engineering Department, University of Pennsylvania, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I79576946"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001362973","display_name":"Laura Pozzi","orcid":"https://orcid.org/0000-0003-1083-8782"},"institutions":[{"id":"https://openalex.org/I57201433","display_name":"Universit\u00e0 della Svizzera italiana","ror":"https://ror.org/03c4atk17","country_code":"CH","type":"education","lineage":["https://openalex.org/I57201433"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Laura Pozzi","raw_affiliation_strings":["[Faculty of Informatics, Universit\u00e0 della Svizzera Italiana, Lugano, Switzerland]"],"raw_orcid":"https://orcid.org/0000-0003-1083-8782","affiliations":[{"raw_affiliation_string":"[Faculty of Informatics, Universit\u00e0 della Svizzera Italiana, Lugano, Switzerland]","institution_ids":["https://openalex.org/I57201433"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"70","issue":null,"first_page":"2013","last_page":"2014"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9767000079154968,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9635999798774719,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.8957444429397583},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8366620540618896},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7593960165977478},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6231616735458374},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5896722674369812},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49958252906799316},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4619446396827698},{"id":"https://openalex.org/keywords/special-section","display_name":"Special section","score":0.4291936159133911},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.41794854402542114},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2217554748058319}],"concepts":[{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.8957444429397583},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8366620540618896},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7593960165977478},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6231616735458374},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5896722674369812},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49958252906799316},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4619446396827698},{"id":"https://openalex.org/C2993458768","wikidata":"https://www.wikidata.org/wiki/Q3477549","display_name":"Special section","level":2,"score":0.4291936159133911},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.41794854402542114},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2217554748058319},{"id":"https://openalex.org/C61696701","wikidata":"https://www.wikidata.org/wiki/Q770766","display_name":"Engineering physics","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:3217082322","is_oa":false,"landing_page_url":"https://dblp.uni-trier.de/db/journals/tc/tc70.html#CardosoDP21","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":"IEEE Transactions on Computers","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.75,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"The":[0,67],"papers":[1],"in":[2,18,20,60],"this":[3],"special":[4],"section":[5],"focus":[6],"on":[7],"compiler":[8],"optimization":[9],"for":[10,54,106],"FPGA-based":[11],"systems.":[12],"Reconfigurable":[13],"computing":[14,22,98],"(RC)":[15],"is":[16],"growing":[17],"importance":[19],"many":[21],"domains":[23],"and":[24,31,81,111],"systems,":[25,44],"from":[26,115],"embedded,":[27],"mobile":[28],"to":[29,63,75],"cloud,":[30],"high-performance":[32],"computing.":[33],"We":[34],"have":[35],"witnessed":[36],"important":[37],"advancements":[38],"regarding":[39,51],"the":[40,64,103],"programming":[41,117],"of":[42,57,69,85],"RC-based":[43],"but":[45],"further":[46],"improvements":[47],"are":[48],"needed,":[49],"especially":[50],"efficient":[52,107],"techniques":[53],"automatic":[55],"mapping":[56],"computations":[58],"described":[59],"high-level":[61,116],"languages":[62],"RC":[65,113],"resources.":[66],"resources":[68],"high-end":[70],"FPGAs":[71],"allow":[72],"these":[73],"devices":[74],"implement":[76],"complex":[77],"Systemson-":[78],"a-Chip":[79],"(SoCs)":[80],"substantial":[82],"computational":[83],"components":[84],"software":[86],"applications,":[87],"e.g.,":[88],"when":[89],"used":[90],"as":[91,95],"hardware":[92],"accelerators":[93],"and/or":[94],"more":[96],"energy-efficient":[97],"platforms.":[99],"This,":[100],"however,":[101],"increases":[102],"continuous":[104],"need":[105],"compilers":[108],"targeting":[109],"FPGAs,":[110],"other":[112],"platforms,":[114],"languages.":[118]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2025-10-10T17:16:08.811792","created_date":"2025-10-10T00:00:00"}
