{"id":"https://openalex.org/W3016284022","doi":"https://doi.org/10.1109/tc.2020.2986970","title":"Karnaugh Map Method for Memristive and Spintronic Asymmetric Basis Logic Functions","display_name":"Karnaugh Map Method for Memristive and Spintronic Asymmetric Basis Logic Functions","publication_year":2020,"publication_date":"2020-04-13","ids":{"openalex":"https://openalex.org/W3016284022","doi":"https://doi.org/10.1109/tc.2020.2986970","mag":"3016284022"},"language":"en","primary_location":{"id":"doi:10.1109/tc.2020.2986970","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2020.2986970","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067440911","display_name":"V. Vyas","orcid":"https://orcid.org/0000-0003-1683-8249"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Vaibhav Vyas","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas at Dallas, Richardson, TX, USA"],"raw_orcid":"https://orcid.org/0000-0003-1683-8249","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108260328","display_name":"Lucian Jiang-Wei","orcid":null},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lucian Jiang-Wei","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas at Dallas, Richardson, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101708067","display_name":"Peng Zhou","orcid":"https://orcid.org/0000-0002-4804-3726"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peng Zhou","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas at Dallas, Richardson, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088513405","display_name":"Xuan Hu","orcid":"https://orcid.org/0000-0002-7337-6637"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xuan Hu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas at Dallas, Richardson, TX, USA"],"raw_orcid":"https://orcid.org/0000-0002-7337-6637","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001887370","display_name":"Joseph S. Friedman","orcid":"https://orcid.org/0000-0001-9847-4455"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joseph S. Friedman","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas at Dallas, Richardson, TX, USA"],"raw_orcid":"https://orcid.org/0000-0001-9847-4455","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5067440911"],"corresponding_institution_ids":["https://openalex.org/I162577319"],"apc_list":null,"apc_paid":null,"fwci":0.5202,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.64203244,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"70","issue":"1","first_page":"128","last_page":"138"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5839456915855408},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5796855688095093},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.532747745513916},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.5076137781143188},{"id":"https://openalex.org/keywords/basis","display_name":"Basis (linear algebra)","score":0.46435096859931946},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3653770685195923},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3351908326148987},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3229420781135559},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24063530564308167},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12719222903251648}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5839456915855408},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5796855688095093},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.532747745513916},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.5076137781143188},{"id":"https://openalex.org/C12426560","wikidata":"https://www.wikidata.org/wiki/Q189569","display_name":"Basis (linear algebra)","level":2,"score":0.46435096859931946},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3653770685195923},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3351908326148987},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3229420781135559},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24063530564308167},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12719222903251648},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.2020.2986970","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2020.2986970","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1486894692","https://openalex.org/W1494109225","https://openalex.org/W2004449536","https://openalex.org/W2025674646","https://openalex.org/W2037906217","https://openalex.org/W2039140951","https://openalex.org/W2043707274","https://openalex.org/W2066280488","https://openalex.org/W2067472652","https://openalex.org/W2074865640","https://openalex.org/W2112181056","https://openalex.org/W2117379410","https://openalex.org/W2122148191","https://openalex.org/W2135340605","https://openalex.org/W2148925416","https://openalex.org/W2162651880","https://openalex.org/W2169757251","https://openalex.org/W2209315239","https://openalex.org/W2220698963","https://openalex.org/W2295866677","https://openalex.org/W2409932422","https://openalex.org/W2510983628","https://openalex.org/W2546945562","https://openalex.org/W2623494632","https://openalex.org/W2741582625","https://openalex.org/W2889491624","https://openalex.org/W2920042105","https://openalex.org/W4231924340","https://openalex.org/W4233183865"],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W2766377030","https://openalex.org/W1977171228","https://openalex.org/W2121963733","https://openalex.org/W2170504327","https://openalex.org/W2041787842","https://openalex.org/W2059422871"],"abstract_inverted_index":{"The":[0],"development":[1,118],"of":[2,13,69,84,92,103,119],"beyond-CMOS":[3],"technologies":[4],"with":[5,62],"alternative":[6],"basis":[7,36,64],"logic":[8,37,65,78,107],"functions":[9,34],"necessitates":[10],"the":[11,40,81,85,93,100,116],"introduction":[12],"novel":[14,121],"design":[15],"automation":[16],"techniques.":[17],"In":[18],"particular,":[19],"recently":[20],"proposed":[21,94],"computing":[22,122],"systems":[23,61],"based":[24],"on":[25],"memristors":[26],"and":[27,42,76,89,105],"bilayer":[28],"avalanche":[29],"spin-diodes":[30],"both":[31],"provide":[32,134],"asymmetric":[33,63],"as":[35,142],"gates":[38],"-":[39],"implication":[41],"inverted-input":[43],"AND,":[44],"respectively.":[45],"This":[46,96],"article":[47],"therefore":[48],"proposes":[49],"a":[50,135],"method":[51,88,97],"by":[52],"which":[53],"Karnaugh":[54,86,129],"maps":[55],"can":[56,133],"be":[57],"directly":[58],"applied":[59],"to":[60,111,144],"functions.":[66],"A":[67],"set":[68],"identities":[70],"is":[71],"defined":[72],"for":[73],"these":[74,120],"memristor":[75],"spintronic":[77,104],"functions,":[79],"enabling":[80],"formal":[82],"demonstration":[83],"map":[87,130],"an":[90],"explanation":[91],"technique.":[95],"thus,":[98],"enables":[99],"direct":[101],"minimization":[102,131],"memristive":[106],"circuits":[108],"without":[109],"translation":[110],"conventional":[112],"Boolean":[113],"algebra,":[114],"facilitating":[115],"further":[117],"paradigms.":[123],"Preliminary":[124],"analyses":[125],"demonstrate":[126],"that":[127],"this":[128],"approach":[132],"28":[136],"percent":[137],"reduction":[138],"in":[139],"step":[140],"count":[141],"compared":[143],"previous":[145],"manual":[146],"optimization.":[147]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}