{"id":"https://openalex.org/W2782573760","doi":"https://doi.org/10.1109/tc.2018.2792445","title":"A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs","display_name":"A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs","publication_year":2018,"publication_date":"2018-01-15","ids":{"openalex":"https://openalex.org/W2782573760","doi":"https://doi.org/10.1109/tc.2018.2792445","mag":"2782573760"},"language":"en","primary_location":{"id":"doi:10.1109/tc.2018.2792445","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2018.2792445","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041754429","display_name":"Ricardo Gonzalez-Toral","orcid":"https://orcid.org/0000-0001-5792-0180"},"institutions":[{"id":"https://openalex.org/I3020445194","display_name":"Universidad Nebrija","ror":"https://ror.org/03tzyrt94","country_code":"ES","type":"education","lineage":["https://openalex.org/I3020445194"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Ricardo Gonzalez-Toral","raw_affiliation_strings":["ARIES Research Center, Universidad Antonio de Nebrija, Madrid, Spain"],"raw_orcid":"https://orcid.org/0000-0001-5792-0180","affiliations":[{"raw_affiliation_string":"ARIES Research Center, Universidad Antonio de Nebrija, Madrid, Spain","institution_ids":["https://openalex.org/I3020445194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080322790","display_name":"Pedro Reviriego","orcid":"https://orcid.org/0000-0003-2540-5234"},"institutions":[{"id":"https://openalex.org/I3020445194","display_name":"Universidad Nebrija","ror":"https://ror.org/03tzyrt94","country_code":"ES","type":"education","lineage":["https://openalex.org/I3020445194"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Pedro Reviriego","raw_affiliation_strings":["ARIES Research Center, Universidad Antonio de Nebrija, Madrid, Spain"],"raw_orcid":"https://orcid.org/0000-0003-2540-5234","affiliations":[{"raw_affiliation_string":"ARIES Research Center, Universidad Antonio de Nebrija, Madrid, Spain","institution_ids":["https://openalex.org/I3020445194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044495372","display_name":"Juan Antonio Maestro","orcid":"https://orcid.org/0000-0001-7133-9026"},"institutions":[{"id":"https://openalex.org/I3020445194","display_name":"Universidad Nebrija","ror":"https://ror.org/03tzyrt94","country_code":"ES","type":"education","lineage":["https://openalex.org/I3020445194"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Juan Antonio Maestro","raw_affiliation_strings":["ARIES Research Center, Universidad Antonio de Nebrija, Madrid, Spain"],"raw_orcid":"https://orcid.org/0000-0001-7133-9026","affiliations":[{"raw_affiliation_string":"ARIES Research Center, Universidad Antonio de Nebrija, Madrid, Spain","institution_ids":["https://openalex.org/I3020445194"]}]},{"author_position":"last","author":{"id":null,"display_name":"Zhen Gao","orcid":"https://orcid.org/0000-0001-9887-1418"},"institutions":[{"id":"https://openalex.org/I162868743","display_name":"Tianjin University","ror":"https://ror.org/012tb2g32","country_code":"CN","type":"education","lineage":["https://openalex.org/I162868743"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhen Gao","raw_affiliation_strings":["School of Electrical and Information Engineering, Tianjin University, Tianjin, China"],"raw_orcid":"https://orcid.org/0000-0001-9887-1418","affiliations":[{"raw_affiliation_string":"School of Electrical and Information Engineering, Tianjin University, Tianjin, China","institution_ids":["https://openalex.org/I162868743"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.01,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.76726979,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":"67","issue":"7","first_page":"1039","last_page":"1045"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7821609973907471},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.756449818611145},{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.6720290780067444},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6046631336212158},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.5402554869651794},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.46675848960876465},{"id":"https://openalex.org/keywords/triple-modular-redundancy","display_name":"Triple modular redundancy","score":0.44191524386405945},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4376559257507324},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.42544087767601013},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3928057551383972},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36634576320648193},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.35778993368148804},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3223382830619812},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.103586345911026}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7821609973907471},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.756449818611145},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.6720290780067444},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6046631336212158},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.5402554869651794},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.46675848960876465},{"id":"https://openalex.org/C196371267","wikidata":"https://www.wikidata.org/wiki/Q3998979","display_name":"Triple modular redundancy","level":3,"score":0.44191524386405945},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4376559257507324},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.42544087767601013},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3928057551383972},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36634576320648193},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35778993368148804},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3223382830619812},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.103586345911026},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.2018.2792445","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2018.2792445","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8","score":0.4300000071525574}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W26016713","https://openalex.org/W67823304","https://openalex.org/W93268216","https://openalex.org/W312415365","https://openalex.org/W641873695","https://openalex.org/W1524576247","https://openalex.org/W1893624440","https://openalex.org/W2042544282","https://openalex.org/W2062470986","https://openalex.org/W2103902557","https://openalex.org/W2103973486","https://openalex.org/W2118832200","https://openalex.org/W2152652532","https://openalex.org/W2167839483","https://openalex.org/W2501354465","https://openalex.org/W2769292965","https://openalex.org/W3149134903","https://openalex.org/W4295678671","https://openalex.org/W6631326754","https://openalex.org/W6842705195"],"related_works":["https://openalex.org/W58658798","https://openalex.org/W3151633427","https://openalex.org/W2212894501","https://openalex.org/W2793465010","https://openalex.org/W3024050170","https://openalex.org/W4293253840","https://openalex.org/W2082438204","https://openalex.org/W2047231322","https://openalex.org/W2188869493","https://openalex.org/W3131896169"],"abstract_inverted_index":{"Soft":[0],"errors":[1,45,57],"are":[2,40,123],"an":[3],"important":[4],"issue":[5],"for":[6,88,176],"SRAM-based":[7,94],"Field":[8],"Programmable":[9],"Gate":[10],"Arrays":[11],"(FPGAs),":[12],"since":[13],"they":[14,24,154],"result":[15],"in":[16,93],"permanent":[17],"alterations":[18],"of":[19,50,69,109,115,120,172,183,191],"the":[20,48,51,60,66,89,102,110,113,116,170,192],"mapped":[21],"circuit":[22],"when":[23],"affect":[25,47],"their":[26,148],"configuration":[27],"memory.":[28],"Concurrent":[29],"Error":[30],"Detection":[31],"(CED)":[32],"techniques,":[33,133],"such":[34],"as":[35],"Dual":[36],"Modular":[37],"Redundancy":[38],"(DMR),":[39],"usually":[41],"employed":[42],"to":[43,55,84,125,129,187],"detect":[44,56],"that":[46,153,182],"performance":[49],"circuit.":[52],"When":[53],"trying":[54],"produced":[58],"on":[59,101,147],"complex":[61,90],"Fast":[62],"Fourier":[63],"Transform":[64],"(FFT),":[65],"Parseval":[67],"Sum":[68],"Squares":[70],"(SoS)":[71],"is":[72,179],"a":[73,82],"widely":[74],"used":[75],"technique.":[76],"In":[77,168],"this":[78],"paper,":[79],"we":[80],"present":[81],"scheme":[83],"implement":[85],"CED":[86],"techniques":[87,97,122,178],"FFT":[91],"implemented":[92],"FPGAs.":[95],"These":[96,132],"perform":[98],"checks":[99],"based":[100],"relationships":[103],"existing":[104],"between":[105],"one":[106],"or":[107],"more":[108],"inputs":[111],"and":[112,137,166],"outputs":[114],"algorithm.":[117],"Three":[118],"examples":[119],"these":[121,177],"provided":[124],"further":[126],"clarify":[127],"how":[128],"construct":[130],"them.":[131],"along":[134],"with":[135,159],"DMR":[136,165],"SoS,":[138,184],"have":[139],"been":[140],"tested":[141],"through":[142],"fault":[143],"injection.":[144],"An":[145],"analysis":[146],"error":[149,174],"detection":[150,157],"capabilities":[151],"shows":[152],"achieve":[155],"high":[156],"rates":[158],"much":[160],"less":[161,188],"resource":[162],"usage":[163],"than":[164,181],"SoS.":[167],"addition,":[169],"number":[171],"false":[173],"detections":[175],"lower":[180],"which":[185],"leads":[186],"unnecessary":[189],"reconfigurations":[190],"device.":[193]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}