{"id":"https://openalex.org/W2780798369","doi":"https://doi.org/10.1109/tc.2017.2786723","title":"A Compositional Approach for Verifying Protocols Running on On-Chip Networks","display_name":"A Compositional Approach for Verifying Protocols Running on On-Chip Networks","publication_year":2017,"publication_date":"2017-12-25","ids":{"openalex":"https://openalex.org/W2780798369","doi":"https://doi.org/10.1109/tc.2017.2786723","mag":"2780798369"},"language":"en","primary_location":{"id":"doi:10.1109/tc.2017.2786723","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2017.2786723","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067135306","display_name":"Freek Verbeek","orcid":"https://orcid.org/0000-0002-6625-1123"},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Freek Verbeek","raw_affiliation_strings":["Systems Software Research Group, Virginia Polytechnic Institute and State University Office of Economic Development, Blacksburg, VA"],"raw_orcid":"https://orcid.org/0000-0002-6625-1123","affiliations":[{"raw_affiliation_string":"Systems Software Research Group, Virginia Polytechnic Institute and State University Office of Economic Development, Blacksburg, VA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109386875","display_name":"Pooria M. Yaghini","orcid":null},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pooria M. Yaghini","raw_affiliation_strings":["Electrical Engineering and Computer Science, University of California, Irvine, CA"],"raw_orcid":"https://orcid.org/0000-0002-0352-0197","affiliations":[{"raw_affiliation_string":"Electrical Engineering and Computer Science, University of California, Irvine, CA","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103169336","display_name":"Ashkan Eghbal","orcid":"https://orcid.org/0000-0003-2816-6953"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ashkan Eghbal","raw_affiliation_strings":["Electrical Engineering and Computer Science, University of California, Irvine, CA"],"raw_orcid":"https://orcid.org/0000-0003-2816-6953","affiliations":[{"raw_affiliation_string":"Electrical Engineering and Computer Science, University of California, Irvine, CA","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5012004974","display_name":"Nader Bagherzadeh","orcid":"https://orcid.org/0000-0001-7216-0546"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nader Bagherzadeh","raw_affiliation_strings":["Electrical Engineering and Computer Science, University of California, Irvine, CA"],"raw_orcid":"https://orcid.org/0000-0001-7216-0546","affiliations":[{"raw_affiliation_string":"Electrical Engineering and Computer Science, University of California, Irvine, CA","institution_ids":["https://openalex.org/I204250578"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1957,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.66206012,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"67","issue":"7","first_page":"905","last_page":"919"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8578720092773438},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.722052812576294},{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.6204401850700378},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.610747754573822},{"id":"https://openalex.org/keywords/protocol","display_name":"Protocol (science)","score":0.578832745552063},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.4340868890285492},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4270945191383362},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.42397594451904297},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41918236017227173},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3428102135658264},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.22068685293197632},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.14862585067749023}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8578720092773438},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.722052812576294},{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.6204401850700378},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.610747754573822},{"id":"https://openalex.org/C2780385302","wikidata":"https://www.wikidata.org/wiki/Q367158","display_name":"Protocol (science)","level":3,"score":0.578832745552063},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.4340868890285492},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4270945191383362},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.42397594451904297},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41918236017227173},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3428102135658264},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.22068685293197632},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.14862585067749023},{"id":"https://openalex.org/C204787440","wikidata":"https://www.wikidata.org/wiki/Q188504","display_name":"Alternative medicine","level":2,"score":0.0},{"id":"https://openalex.org/C142724271","wikidata":"https://www.wikidata.org/wiki/Q7208","display_name":"Pathology","level":1,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tc.2017.2786723","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2017.2786723","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},{"id":"pmh:oai:research.ou.nl:publications/b9368d61-2701-4d5c-9b81-7a4296123afb","is_oa":false,"landing_page_url":"https://hdl.handle.net/1820/b9368d61-2701-4d5c-9b81-7a4296123afb","pdf_url":null,"source":{"id":"https://openalex.org/S4306401002","display_name":"DSpace (Open University in the Netherlands)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I7876267","host_organization_name":"Open University of the Netherlands","host_organization_lineage":["https://openalex.org/I7876267"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Verbeek, F, Yaghini, P M, Eghbal, A & Bagherzadeh, N 2018, 'A Compositional Approach for Verifying Protocols Running on On-Chip Networks', Ieee Transactions on Computers, vol. 67, no. 7, pp. 905-919. https://doi.org/10.1109/TC.2017.2786723","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:ou:oai:research.ou.nl:publications/b9368d61-2701-4d5c-9b81-7a4296123afb","is_oa":false,"landing_page_url":"https://research.ou.nl/en/publications/b9368d61-2701-4d5c-9b81-7a4296123afb","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Ieee Transactions on Computers, 67(7), 905 - 919. IEEE COMPUTER SOC","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":51,"referenced_works":["https://openalex.org/W192373886","https://openalex.org/W233122475","https://openalex.org/W830286254","https://openalex.org/W1496710542","https://openalex.org/W1498432697","https://openalex.org/W1528837436","https://openalex.org/W1532374416","https://openalex.org/W1586167239","https://openalex.org/W1595528047","https://openalex.org/W1719912185","https://openalex.org/W1879996931","https://openalex.org/W1962072139","https://openalex.org/W1965237160","https://openalex.org/W1983371115","https://openalex.org/W1984957636","https://openalex.org/W2015146732","https://openalex.org/W2024390509","https://openalex.org/W2039035430","https://openalex.org/W2041152728","https://openalex.org/W2062390281","https://openalex.org/W2075201692","https://openalex.org/W2080593426","https://openalex.org/W2081911632","https://openalex.org/W2082471399","https://openalex.org/W2082636948","https://openalex.org/W2095319311","https://openalex.org/W2095597489","https://openalex.org/W2097027683","https://openalex.org/W2114658430","https://openalex.org/W2115309705","https://openalex.org/W2121563512","https://openalex.org/W2124552466","https://openalex.org/W2130183852","https://openalex.org/W2137865376","https://openalex.org/W2147657366","https://openalex.org/W2148392844","https://openalex.org/W2154323564","https://openalex.org/W2161380643","https://openalex.org/W2163947040","https://openalex.org/W2166423938","https://openalex.org/W2238800873","https://openalex.org/W2471498569","https://openalex.org/W2522679276","https://openalex.org/W2529702211","https://openalex.org/W2571119887","https://openalex.org/W2728730510","https://openalex.org/W4244048786","https://openalex.org/W4245160202","https://openalex.org/W6623160810","https://openalex.org/W6635761747","https://openalex.org/W6727779222"],"related_works":["https://openalex.org/W1539379314","https://openalex.org/W397120980","https://openalex.org/W1528537929","https://openalex.org/W3021060317","https://openalex.org/W2971368204","https://openalex.org/W2074817166","https://openalex.org/W2149817600","https://openalex.org/W2337418885","https://openalex.org/W4207012101","https://openalex.org/W2751820975"],"abstract_inverted_index":{"In":[0],"modern":[1],"many-core":[2],"architectures,":[3],"advanced":[4,140],"on-chip":[5],"networks":[6],"provide":[7],"the":[8,13,18,23,42,46,49,94,119],"means":[9],"of":[10,22,139],"communication":[11],"for":[12],"cores.":[14,30,120],"This":[15,51,74],"greatly":[16],"complicates":[17],"design":[19],"and":[20,48,68,90,134],"verification":[21],"cache":[24],"coherence":[25],"protocols":[26,128],"deployed":[27],"by":[28,112],"those":[29],"A":[31],"common":[32],"approach":[33],"to":[34,40,125],"deal":[35],"with":[36,142],"this":[37,123],"complexity":[38],"is":[39,101,110],"decompose":[41],"whole":[43],"system":[44,95],"into":[45],"protocol":[47,67],"network.":[50],"decomposition":[52,109],"is,":[53],"however,":[54],"not":[55],"always":[56],"possible.":[57],"For":[58],"example,":[59],"unexpected":[60],"deadlocks":[61],"can":[62],"emerge":[63],"when":[64],"a":[65,69,77,83,88,97],"deadlock-free":[66,70],"network":[71],"are":[72],"combined.":[73],"paper":[75],"proposes":[76],"compositional":[78],"methodology:":[79],"prove":[80,85],"properties":[81,86,92],"over":[82,87,93],"network,":[84],"protocol,":[89],"infer":[91],"as":[96,130],"whole.":[98],"Our":[99],"methodology":[100,124],"based":[102],"on":[103,137],"theorems":[104],"that":[105,107],"show":[106],"such":[108,129],"possible":[111],"having":[113],"sufficiently":[114],"large":[115],"local":[116],"buffers":[117],"at":[118],"We":[121],"apply":[122],"verify":[126],"several":[127],"MI,":[131],"MSI,":[132],"MESI":[133],"MEUSI":[135],"running":[136],"top":[138],"interconnects":[141],"adaptive":[143],"routing.":[144]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2026-07-28T07:46:37.118299","created_date":"2025-10-10T00:00:00"}
