{"id":"https://openalex.org/W2769311538","doi":"https://doi.org/10.1109/tc.2017.2776908","title":"Lightweight Hardware Transactional Memory for GPU Scratchpad Memory","display_name":"Lightweight Hardware Transactional Memory for GPU Scratchpad Memory","publication_year":2017,"publication_date":"2017-11-23","ids":{"openalex":"https://openalex.org/W2769311538","doi":"https://doi.org/10.1109/tc.2017.2776908","mag":"2769311538"},"language":"en","primary_location":{"id":"doi:10.1109/tc.2017.2776908","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2017.2776908","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039157507","display_name":"Alejandro Villegas","orcid":"https://orcid.org/0000-0002-0269-2640"},"institutions":[{"id":"https://openalex.org/I3160204658","display_name":"Technological Corporation of Andalusia","ror":"https://ror.org/03a54va40","country_code":"ES","type":"government","lineage":["https://openalex.org/I3160204658"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Alejandro Villegas","raw_affiliation_strings":["Department of Computer Architecture, Andaluc\u00eda Tech, M\u00e1laga, Spain"],"raw_orcid":"https://orcid.org/0000-0002-0269-2640","affiliations":[{"raw_affiliation_string":"Department of Computer Architecture, Andaluc\u00eda Tech, M\u00e1laga, Spain","institution_ids":["https://openalex.org/I3160204658"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041029240","display_name":"Rafael Asenjo","orcid":"https://orcid.org/0000-0002-1570-3863"},"institutions":[{"id":"https://openalex.org/I3160204658","display_name":"Technological Corporation of Andalusia","ror":"https://ror.org/03a54va40","country_code":"ES","type":"government","lineage":["https://openalex.org/I3160204658"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Rafael Asenjo","raw_affiliation_strings":["Department of Computer Architecture, Andaluc\u00eda Tech, M\u00e1laga, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Architecture, Andaluc\u00eda Tech, M\u00e1laga, Spain","institution_ids":["https://openalex.org/I3160204658"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038271291","display_name":"\u00c1ngeles Navarro","orcid":"https://orcid.org/0000-0002-4140-2589"},"institutions":[{"id":"https://openalex.org/I3160204658","display_name":"Technological Corporation of Andalusia","ror":"https://ror.org/03a54va40","country_code":"ES","type":"government","lineage":["https://openalex.org/I3160204658"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Angeles Navarro","raw_affiliation_strings":["Department of Computer Architecture, Andaluc\u00eda Tech, M\u00e1laga, Spain"],"raw_orcid":"https://orcid.org/0000-0002-4140-2589","affiliations":[{"raw_affiliation_string":"Department of Computer Architecture, Andaluc\u00eda Tech, M\u00e1laga, Spain","institution_ids":["https://openalex.org/I3160204658"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032105032","display_name":"\u00d3scar Plata","orcid":"https://orcid.org/0000-0003-2233-0011"},"institutions":[{"id":"https://openalex.org/I3160204658","display_name":"Technological Corporation of Andalusia","ror":"https://ror.org/03a54va40","country_code":"ES","type":"government","lineage":["https://openalex.org/I3160204658"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Oscar Plata","raw_affiliation_strings":["Department of Computer Architecture, Andaluc\u00eda Tech, M\u00e1laga, Spain"],"raw_orcid":"https://orcid.org/0000-0003-2233-0011","affiliations":[{"raw_affiliation_string":"Department of Computer Architecture, Andaluc\u00eda Tech, M\u00e1laga, Spain","institution_ids":["https://openalex.org/I3160204658"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061128237","display_name":"David Kaeli","orcid":"https://orcid.org/0000-0002-5692-0151"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Kaeli","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Northeastern University, Boston, MA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Northeastern University, Boston, MA","institution_ids":["https://openalex.org/I12912129"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.5925,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.85829384,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"67","issue":"6","first_page":"816","last_page":"829"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.902008056640625},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7043891549110413},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.5752147436141968},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.5661091804504395},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.5183895230293274},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.5021922588348389},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5004024505615234},{"id":"https://openalex.org/keywords/memory-model","display_name":"Memory model","score":0.4628739655017853},{"id":"https://openalex.org/keywords/distributed-memory","display_name":"Distributed memory","score":0.4305627942085266},{"id":"https://openalex.org/keywords/transactional-memory","display_name":"Transactional memory","score":0.4198802411556244},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.41505351662635803},{"id":"https://openalex.org/keywords/graphics-processing-unit","display_name":"Graphics processing unit","score":0.41162747144699097},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.31303760409355164},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3024927079677582},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.1546168029308319},{"id":"https://openalex.org/keywords/database-transaction","display_name":"Database transaction","score":0.10200688242912292}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.902008056640625},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7043891549110413},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.5752147436141968},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.5661091804504395},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.5183895230293274},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.5021922588348389},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5004024505615234},{"id":"https://openalex.org/C12186640","wikidata":"https://www.wikidata.org/wiki/Q6815743","display_name":"Memory model","level":3,"score":0.4628739655017853},{"id":"https://openalex.org/C91481028","wikidata":"https://www.wikidata.org/wiki/Q1054686","display_name":"Distributed memory","level":3,"score":0.4305627942085266},{"id":"https://openalex.org/C134277064","wikidata":"https://www.wikidata.org/wiki/Q878206","display_name":"Transactional memory","level":3,"score":0.4198802411556244},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.41505351662635803},{"id":"https://openalex.org/C2779851693","wikidata":"https://www.wikidata.org/wiki/Q183484","display_name":"Graphics processing unit","level":2,"score":0.41162747144699097},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.31303760409355164},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3024927079677582},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.1546168029308319},{"id":"https://openalex.org/C75949130","wikidata":"https://www.wikidata.org/wiki/Q848010","display_name":"Database transaction","level":2,"score":0.10200688242912292},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.2017.2776908","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2017.2776908","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320311265","display_name":"Universidad de M\u00e1laga","ror":"https://ror.org/036b2ww28"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W76990466","https://openalex.org/W1715366078","https://openalex.org/W1974165977","https://openalex.org/W1992418748","https://openalex.org/W2041356909","https://openalex.org/W2078994750","https://openalex.org/W2080592089","https://openalex.org/W2101209730","https://openalex.org/W2103742924","https://openalex.org/W2113751407","https://openalex.org/W2122106801","https://openalex.org/W2123845384","https://openalex.org/W2129444820","https://openalex.org/W2138218143","https://openalex.org/W2163654949","https://openalex.org/W2165791323","https://openalex.org/W2169810797","https://openalex.org/W2227386419","https://openalex.org/W2335340700","https://openalex.org/W2415865954","https://openalex.org/W2545744347","https://openalex.org/W2567524601","https://openalex.org/W2611473431","https://openalex.org/W2692263070","https://openalex.org/W3147336131","https://openalex.org/W4238433345","https://openalex.org/W4244583165","https://openalex.org/W4298077439","https://openalex.org/W6637912555"],"related_works":["https://openalex.org/W2099709763","https://openalex.org/W1839004754","https://openalex.org/W4317827391","https://openalex.org/W2186451538","https://openalex.org/W2182797201","https://openalex.org/W2124489231","https://openalex.org/W120656789","https://openalex.org/W4233212676","https://openalex.org/W2114532962","https://openalex.org/W2078898826"],"abstract_inverted_index":{"Graphics":[0],"Processing":[1],"Units":[2],"(GPUs)":[3],"have":[4],"become":[5],"the":[6,14,41,44,59,71,87,106,137,149,166,169,172],"accelerator":[7],"of":[8,16,18,58,73,105,168],"choice":[9],"for":[10,131,141],"data-parallel":[11],"applications,":[12],"enabling":[13],"execution":[15,89],"thousands":[17],"threads":[19,42],"in":[20,43,148,175],"a":[21,34,49,56,67,124],"Single":[22],"Instruction":[23],"-":[24],"Multiple":[25],"Thread":[26],"(SIMT)":[27],"fashion.":[28],"Using":[29],"OpenCL":[30],"terminology,":[31],"GPUs":[32],"offer":[33],"global":[35,84],"memory":[36,51,65,111,129,151],"space":[37,52],"shared":[38,53,97],"by":[39,54],"all":[40],"GPU,":[45],"as":[46,48,66,81,123],"well":[47],"local":[50,64,110,133],"only":[55],"subset":[57],"threads.":[60],"Programmers":[61],"can":[62,161],"use":[63],"scratchpad":[68],"to":[69,77,83,95,114,164,184],"improve":[70],"performance":[72],"their":[74],"applications":[75],"due":[76],"its":[78],"lower":[79,107],"latency":[80,108],"compared":[82],"memory.":[85,134],"In":[86],"SIMT":[88],"model,":[90],"data":[91,98],"locking":[92],"mechanisms":[93,159],"used":[94,163],"protect":[96],"limit":[99],"scalability.":[100],"To":[101,135],"take":[102],"full":[103],"advantage":[104],"that":[109,160],"affords,":[112],"and":[113,126],"provide":[115],"an":[116],"efficient":[117,127],"synchronization":[118],"mechanism,":[119],"we":[120],"propose":[121],"GPU-LocalTM":[122,144,154,179],"lightweight":[125],"transactional":[128,146],"(TM)":[130],"GPU":[132],"minimize":[136],"storage":[138],"resources":[139],"required":[140],"TM":[142],"support,":[143],"allocates":[145],"metadata":[147],"existing":[150],"resources.":[152],"Additionally,":[153],"implements":[155],"different":[156],"conflict":[157],"detection":[158],"be":[162],"match":[165],"characteristics":[167],"application.":[170],"For":[171],"workloads":[173],"studied":[174],"our":[176],"simulation-based":[177],"evaluation,":[178],"provides":[180],"from":[181],"1.1X":[182],"up":[183],"100X":[185],"speedup":[186],"over":[187],"serialized":[188],"critical":[189],"sections.":[190]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2}],"updated_date":"2026-07-18T07:39:51.176621","created_date":"2025-10-10T00:00:00"}
