{"id":"https://openalex.org/W2615329347","doi":"https://doi.org/10.1109/tc.2017.2705141","title":"A Dual-Clock Multiple-Queue Shared Buffer","display_name":"A Dual-Clock Multiple-Queue Shared Buffer","publication_year":2017,"publication_date":"2017-05-17","ids":{"openalex":"https://openalex.org/W2615329347","doi":"https://doi.org/10.1109/tc.2017.2705141","mag":"2615329347"},"language":"en","primary_location":{"id":"doi:10.1109/tc.2017.2705141","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2017.2705141","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052539927","display_name":"\u0391\u03bd\u03b1\u03c3\u03c4\u03ac\u03c3\u03b9\u03bf\u03c2 \u03a8\u03b1\u03c1\u03c1\u03ac\u03c2","orcid":"https://orcid.org/0000-0001-6151-9242"},"institutions":[{"id":"https://openalex.org/I147962203","display_name":"Democritus University of Thrace","ror":"https://ror.org/03bfqnx40","country_code":"GR","type":"education","lineage":["https://openalex.org/I147962203"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Anastasios Psarras","raw_affiliation_strings":["Electrical and Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020784491","display_name":"Michalis Paschou","orcid":null},"institutions":[{"id":"https://openalex.org/I147962203","display_name":"Democritus University of Thrace","ror":"https://ror.org/03bfqnx40","country_code":"GR","type":"education","lineage":["https://openalex.org/I147962203"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Michalis Paschou","raw_affiliation_strings":["Electrical and Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035714231","display_name":"Chrysostomos Nicopoulos","orcid":"https://orcid.org/0000-0001-6389-6068"},"institutions":[{"id":"https://openalex.org/I34771391","display_name":"University of Cyprus","ror":"https://ror.org/02qjrjx09","country_code":"CY","type":"education","lineage":["https://openalex.org/I34771391"]}],"countries":["CY"],"is_corresponding":false,"raw_author_name":"Chrysostomos Nicopoulos","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Cyprus, Nicosia, Cyprus"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Cyprus, Nicosia, Cyprus","institution_ids":["https://openalex.org/I34771391"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074704256","display_name":"Giorgos Dimitrakopoulos","orcid":"https://orcid.org/0000-0003-3688-7865"},"institutions":[{"id":"https://openalex.org/I147962203","display_name":"Democritus University of Thrace","ror":"https://ror.org/03bfqnx40","country_code":"GR","type":"education","lineage":["https://openalex.org/I147962203"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Giorgos Dimitrakopoulos","raw_affiliation_strings":["Electrical and Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Democritus University of Thrace, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5052539927"],"corresponding_institution_ids":["https://openalex.org/I147962203"],"apc_list":null,"apc_paid":null,"fwci":0.6216,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.71060275,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"66","issue":"10","first_page":"1809","last_page":"1815"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8351582288742065},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6756145358085632},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.6657198667526245},{"id":"https://openalex.org/keywords/queue","display_name":"Queue","score":0.6332117915153503},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.5612291097640991},{"id":"https://openalex.org/keywords/queueing-theory","display_name":"Queueing theory","score":0.5471413135528564},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.5393677949905396},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5183842778205872},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.4573372006416321},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.443070650100708},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.42744898796081543},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3510885536670685},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3368687629699707},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.336056113243103},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3340902328491211},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.26140496134757996},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.2209426760673523},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.16104432940483093},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12635570764541626},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.08791786432266235},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.08761709928512573},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.08749911189079285}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8351582288742065},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6756145358085632},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.6657198667526245},{"id":"https://openalex.org/C160403385","wikidata":"https://www.wikidata.org/wiki/Q220543","display_name":"Queue","level":2,"score":0.6332117915153503},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.5612291097640991},{"id":"https://openalex.org/C22684755","wikidata":"https://www.wikidata.org/wiki/Q847526","display_name":"Queueing theory","level":2,"score":0.5471413135528564},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.5393677949905396},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5183842778205872},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.4573372006416321},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.443070650100708},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.42744898796081543},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3510885536670685},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3368687629699707},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.336056113243103},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3340902328491211},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.26140496134757996},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.2209426760673523},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.16104432940483093},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12635570764541626},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.08791786432266235},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.08761709928512573},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.08749911189079285},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.2017.2705141","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2017.2705141","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.41999998688697815,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1589885802","https://openalex.org/W1964963116","https://openalex.org/W2003594374","https://openalex.org/W2047779031","https://openalex.org/W2096383657","https://openalex.org/W2104674486","https://openalex.org/W2119616711","https://openalex.org/W2126647846","https://openalex.org/W2143906836","https://openalex.org/W2149265201","https://openalex.org/W2155597158","https://openalex.org/W2347079473","https://openalex.org/W2410088626","https://openalex.org/W3209970425"],"related_works":["https://openalex.org/W1917576147","https://openalex.org/W2109520798","https://openalex.org/W2292909929","https://openalex.org/W1966845705","https://openalex.org/W1497331638","https://openalex.org/W2386718233","https://openalex.org/W2371965169","https://openalex.org/W2006392656","https://openalex.org/W4379649967","https://openalex.org/W2147289961"],"abstract_inverted_index":{"Multiple":[0],"parallel":[1],"queues":[2,22],"are":[3,9,23,124],"versatile":[4],"hardware":[5,94,116],"data":[6],"structures":[7],"that":[8,32,55,77],"extensively":[10],"used":[11],"in":[12,64,91],"modern":[13],"digital":[14],"systems.":[15],"To":[16],"achieve":[17],"maximum":[18],"scalability,":[19],"the":[20,34,38,79,104],"multiple":[21],"built":[24],"on":[25,43,50],"top":[26],"of":[27,81,119],"a":[28,44,74,92,111],"dynamically-allocated":[29,51],"shared":[30,53,71],"buffer":[31,35,72],"allocates":[33],"space":[36],"to":[37,62,98,109,121],"various":[39],"active":[40],"queues,":[41],"based":[42],"linked-list":[45],"organization.":[46],"This":[47],"work":[48],"focuses":[49],"multiple-queue":[52,102],"buffers":[54],"allow":[56],"their":[57],"read":[58],"and":[59,88],"write":[60],"ports":[61],"operate":[63],"different":[65],"clock":[66,86],"domains.":[67],"The":[68],"proposed":[69],"dual-clock":[70,101],"follows":[73],"tightly-coupled":[75],"organization":[76],"merges":[78],"tasks":[80],"signal":[82],"synchronization":[83],"across":[84],"asynchronous":[85],"domains":[87],"queueing":[89],"(buffering),":[90],"common":[93],"module.":[95],"When":[96],"compared":[97],"other":[99],"state-of-the-art":[100],"designs,":[103],"new":[105],"architecture":[106],"is":[107],"demonstrated":[108],"yield":[110],"substantially":[112],"lower-cost":[113],"implementation.":[114],"Specifically,":[115],"area":[117],"savings":[118],"up":[120],"55":[122],"percent":[123],"achieved,":[125],"while":[126],"still":[127],"supporting":[128],"full-throughput":[129],"operation.":[130]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
