{"id":"https://openalex.org/W2532094356","doi":"https://doi.org/10.1109/tc.2016.2621045","title":"Design and Applications for Embedded Networks-on-Chip on FPGAs","display_name":"Design and Applications for Embedded Networks-on-Chip on FPGAs","publication_year":2016,"publication_date":"2016-10-25","ids":{"openalex":"https://openalex.org/W2532094356","doi":"https://doi.org/10.1109/tc.2016.2621045","mag":"2532094356"},"language":"en","primary_location":{"id":"doi:10.1109/tc.2016.2621045","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2016.2621045","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010814272","display_name":"Mohamed S. Abdelfattah","orcid":"https://orcid.org/0000-0002-4568-8932"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Mohamed S. Abdelfattah","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071905570","display_name":"Andrew Bitar","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Andrew Bitar","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030184404","display_name":"Vaughn Betz","orcid":"https://orcid.org/0000-0003-0528-6493"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Vaughn Betz","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.1817,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.82556515,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"66","issue":"6","first_page":"1008","last_page":"1021"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10714","display_name":"Software-Defined Networks and 5G","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7893079519271851},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7669638395309448},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6988310813903809},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5719655156135559},{"id":"https://openalex.org/keywords/ethernet","display_name":"Ethernet","score":0.5354013442993164},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.5033091902732849},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.45312124490737915},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3597322106361389},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1908228099346161}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7893079519271851},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7669638395309448},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6988310813903809},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5719655156135559},{"id":"https://openalex.org/C172173386","wikidata":"https://www.wikidata.org/wiki/Q79984","display_name":"Ethernet","level":2,"score":0.5354013442993164},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.5033091902732849},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45312124490737915},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3597322106361389},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1908228099346161}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.2016.2621045","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2016.2621045","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.550000011920929,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1501077214","https://openalex.org/W1997700518","https://openalex.org/W2013272814","https://openalex.org/W2026164946","https://openalex.org/W2026844540","https://openalex.org/W2046105216","https://openalex.org/W2061488635","https://openalex.org/W2118231264","https://openalex.org/W2120538858","https://openalex.org/W2125560635","https://openalex.org/W2131166199","https://openalex.org/W2134519279","https://openalex.org/W2142987071","https://openalex.org/W2147118406","https://openalex.org/W2170293694","https://openalex.org/W2171825402","https://openalex.org/W2264331490","https://openalex.org/W2281100802","https://openalex.org/W2922814486","https://openalex.org/W4256629673","https://openalex.org/W6665513741"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W4200391368","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W4863605","https://openalex.org/W4285287318","https://openalex.org/W2784141701","https://openalex.org/W2138821532","https://openalex.org/W1978899622"],"abstract_inverted_index":{"Field-programmable":[0],"gate-arrays":[1],"(FPGAs)":[2],"have":[3],"evolved":[4],"to":[5,60,68,73,91,118,172,183],"include":[6],"embedded":[7,57,99,111,135,160],"memory,":[8],"high-speed":[9],"I/O":[10],"interfaces":[11,67],"and":[12,19,24,47,77,82,85,149,153,178,199],"processors,":[13],"making":[14],"them":[15],"both":[16],"more":[17,154,175,200],"efficient":[18,83,201],"easier-to-use":[20],"for":[21],"compute":[22],"acceleration":[23],"networking":[25],"applications.":[26],"However,":[27],"implementing":[28],"on-chip":[29],"communication":[30],"is":[31,196],"still":[32],"a":[33,70,80,164,189],"designer's":[34],"burden":[35],"wherein":[36],"custom":[37,66],"system-level":[38,62],"buses":[39],"are":[40],"implemented":[41],"using":[42,109],"the":[43,74,88,106,159],"fine-grained":[44],"FPGA":[45,75,94],"logic":[46],"interconnect":[48],"fabric.":[49],"Instead,":[50],"we":[51,157,187],"propose":[52],"augmenting":[53],"FPGAs":[54],"with":[55,97,129],"an":[56,98,110,134],"network-on-chip":[58],"(NoC)":[59],"implement":[61,92],"communication.":[63],"We":[64,113],"design":[65,95,151,188],"connect":[69],"packet-switched":[71],"NoC":[72,136,161],"fabric":[76],"I/Os":[78],"in":[79,162],"configurable":[81],"way":[84],"then":[86],"define":[87],"necessary":[89],"conditions":[90],"common":[93],"styles":[96],"NoC.":[100,112],"Four":[101],"application":[102,126],"case":[103,127],"studies":[104],"highlight":[105],"advantages":[107],"of":[108,143],"show":[114],"that":[115,133,168,195],"access":[116],"latency":[117],"external":[119],"memory":[120],"can":[121,169],"be":[122],"~1.5\u00d7":[123],"lower.":[124],"Our":[125],"study":[128],"image":[130],"compression":[131],"shows":[132],"improves":[137],"frequency":[138],"by":[139,147],"10-80%,":[140],"reduces":[141],"utilization":[142],"scarce":[144],"long":[145],"wires":[146],"40%":[148],"makes":[150],"easier":[152],"predictable.":[155],"Additionally,":[156],"leverage":[158],"creating":[163],"programmable":[165],"Ethernet":[166],"switch":[167],"support":[170],"up":[171],"819":[173],"Gb/s-5\u00d7":[174],"switching":[176],"bandwidth":[177],"3\u00d7":[179],"lower":[180],"area":[181],"compared":[182],"previous":[184],"work.":[185],"Finally,":[186],"400":[190],"Gb/s":[191],"NoC-based":[192],"packet":[193,205],"processor":[194],"very":[197],"flexible":[198],"than":[202],"other":[203],"FPGA-based":[204],"processors.":[206]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}