{"id":"https://openalex.org/W2299560900","doi":"https://doi.org/10.1109/tc.2015.2506581","title":"Cache Design with Domain Wall Memory","display_name":"Cache Design with Domain Wall Memory","publication_year":2015,"publication_date":"2015-12-09","ids":{"openalex":"https://openalex.org/W2299560900","doi":"https://doi.org/10.1109/tc.2015.2506581","mag":"2299560900"},"language":"en","primary_location":{"id":"doi:10.1109/tc.2015.2506581","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2015.2506581","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045219356","display_name":"Rangharajan Venkatesan","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Rangharajan Venkatesan","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014678802","display_name":"Vivek Kozhikkottu","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vivek J. Kozhikkottu","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019643842","display_name":"Mrigank Sharad","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mrigank Sharad","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085682261","display_name":"Charles Augustine","orcid":"https://orcid.org/0000-0001-8892-6286"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Charles Augustine","raw_affiliation_strings":["Circuit Research Labs, Intel Corporation, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuit Research Labs, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091408102","display_name":"Arijit Raychowdhury","orcid":"https://orcid.org/0000-0001-8391-0576"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arijit Raychowdhury","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031161187","display_name":"Kaushik Roy","orcid":"https://orcid.org/0009-0002-3375-2877"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kaushik Roy","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065766721","display_name":"Anand Raghunathan","orcid":"https://orcid.org/0000-0002-4624-564X"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anand Raghunathan","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5045219356"],"corresponding_institution_ids":["https://openalex.org/I219193219"],"apc_list":null,"apc_paid":null,"fwci":3.8603,"has_fulltext":false,"cited_by_count":31,"citation_normalized_percentile":{"value":0.94190754,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"65","issue":"4","first_page":"1010","last_page":"1024"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10049","display_name":"Magnetic properties of thin films","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/3107","display_name":"Atomic and Molecular Physics, and Optics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8397147059440613},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6980159282684326},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.6021589040756226},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5783702731132507},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.5186759233474731},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5095891952514648},{"id":"https://openalex.org/keywords/access-time","display_name":"Access time","score":0.4775175154209137},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.45621979236602783},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.452304869890213},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.447272390127182},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.43391916155815125},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3019525110721588}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8397147059440613},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6980159282684326},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.6021589040756226},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5783702731132507},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.5186759233474731},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5095891952514648},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.4775175154209137},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.45621979236602783},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.452304869890213},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.447272390127182},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.43391916155815125},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3019525110721588}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.2015.2506581","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2015.2506581","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"},{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"},{"id":"https://openalex.org/F4320322907","display_name":"Gutenberg Forschungskolleg","ror":"https://ror.org/023b0x485"},{"id":"https://openalex.org/F4320331888","display_name":"Microelectronics Advanced Research Corporation","ror":"https://ror.org/047z4n946"},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":56,"referenced_works":["https://openalex.org/W1599561009","https://openalex.org/W1968480751","https://openalex.org/W1968686941","https://openalex.org/W1971543343","https://openalex.org/W1981443800","https://openalex.org/W1983739214","https://openalex.org/W1992775315","https://openalex.org/W2003390915","https://openalex.org/W2005242923","https://openalex.org/W2009481135","https://openalex.org/W2011443263","https://openalex.org/W2018384083","https://openalex.org/W2029083842","https://openalex.org/W2033188264","https://openalex.org/W2034097727","https://openalex.org/W2045865593","https://openalex.org/W2047379549","https://openalex.org/W2048588974","https://openalex.org/W2061941096","https://openalex.org/W2063517113","https://openalex.org/W2064977311","https://openalex.org/W2065558271","https://openalex.org/W2072656003","https://openalex.org/W2078760460","https://openalex.org/W2084007230","https://openalex.org/W2087461437","https://openalex.org/W2097823832","https://openalex.org/W2102449048","https://openalex.org/W2104225326","https://openalex.org/W2106450710","https://openalex.org/W2109640656","https://openalex.org/W2116826022","https://openalex.org/W2121290756","https://openalex.org/W2125305952","https://openalex.org/W2135393827","https://openalex.org/W2136316949","https://openalex.org/W2142276919","https://openalex.org/W2142715748","https://openalex.org/W2146245483","https://openalex.org/W2147539449","https://openalex.org/W2148831941","https://openalex.org/W2154553951","https://openalex.org/W2155551886","https://openalex.org/W2170666978","https://openalex.org/W2464177207","https://openalex.org/W3102163985","https://openalex.org/W3139006581","https://openalex.org/W3145738314","https://openalex.org/W3147620158","https://openalex.org/W4240165677","https://openalex.org/W4254159549","https://openalex.org/W6635732093","https://openalex.org/W6653237175","https://openalex.org/W6682854596","https://openalex.org/W6684763460","https://openalex.org/W6719768283"],"related_works":["https://openalex.org/W2217292995","https://openalex.org/W2115782696","https://openalex.org/W3145643808","https://openalex.org/W2966447112","https://openalex.org/W2363409354","https://openalex.org/W109043737","https://openalex.org/W2262128607","https://openalex.org/W4246122698","https://openalex.org/W2988244725","https://openalex.org/W4226255854"],"abstract_inverted_index":{"Domain":[0],"wall":[1,168],"memory":[2,9,35,92],"(DWM)":[3],"is":[4,74],"a":[5,24,112,136,161,208,228,258],"recently":[6],"developed":[7],"spin-based":[8,91,131],"technology":[10],"in":[11,32,111,175,198,227,242,281,299],"which":[12],"several":[13],"bits":[14,109,226],"of":[15,23,60,67,104,129,195,261,272],"data":[16],"are":[17,188],"densely":[18],"packed":[19],"into":[20],"the":[21,58,63,77,101,108,125,152,178,191,199,203,218,234,240,243],"domains":[22],"ferromagnetic":[25],"wire.":[26],"DWM":[27,61,184,229,250],"has":[28,44],"shown":[29],"great":[30],"promise":[31],"enabling":[33],"non-volatile":[34],"with":[36,274,307],"very":[37],"high":[38],"density":[39,84],"and":[40,43,50,89,117,144,212,251,278,301],"energy":[41,270,304],"efficiency,":[42],"been":[45],"explored":[46],"for":[47],"secondary":[48],"storage":[49],"off-chip":[51],"memory.":[52],"In":[53,121],"this":[54],"work,":[55],"we":[56,155,181,206],"explore":[57],"use":[59],"within":[62],"on-chip":[64],"cache":[65,138,200,210,244],"hierarchy":[66,245],"general":[68],"purpose":[69],"computing":[70],"platforms.":[71],"Our":[72],"work":[73],"motivated":[75],"by":[76,159],"fact":[78],"that":[79,140,187,216,233],"DWMs":[80,98,123],"enable":[81],"much":[82],"higher":[83],"compared":[85,283],"to":[86,107,115,147,170,190,225,246,284,290],"SRAM,":[87],"DRAM,":[88],"other":[90,130],"technologies":[93],"such":[94],"as":[95],"STT-MRAM.":[96],"However,":[97],"also":[99],"pose":[100],"unique":[102],"challenge":[103],"serial":[105,223],"access":[106,119,224],"stored":[110],"cell,":[113],"leading":[114],"large":[116],"variable":[118],"latencies.":[120],"addition,":[122],"share":[124],"inherent":[126],"write":[127,157,163],"inefficiency":[128],"memories.":[132],"We":[133,231],"propose":[134,182,207],"TapeCache,":[135],"DWM-based":[137],"design":[139],"employs":[141],"device,":[142],"circuit,":[143],"architectural":[145,193],"techniques":[146],"address":[148],"these":[149],"challenges.":[150],"At":[151,177,202],"device":[153],"level,":[154,180,205],"perform":[156],"optimization":[158],"employing":[160],"new":[162,209],"mechanism":[164],"based":[165],"on":[166],"domain":[167],"shifts":[169],"achieve":[171],"fast,":[172],"energy-efficient":[173],"writes":[174],"DWM.":[176],"circuit":[179],"different":[183,196],"bit-cell":[185],"designs":[186],"tailored":[189],"distinct":[192],"requirements":[194],"levels":[197,241],"hierarchy.":[201],"architecture":[204],"organization":[211],"suitable":[213],"management":[214],"policies":[215],"mitigate":[217],"performance":[219,277,310],"penalty":[220],"arising":[221],"from":[222,253],"cell.":[230],"show":[232],"holistic":[235],"device-circuit-architecture":[236],"co-design":[237],"enables":[238],"all":[239],"be":[247],"realized":[248],"using":[249],"benefit":[252],"its":[254],"improved":[255],"density.":[256],"Over":[257],"wide":[259],"range":[260],"SPEC":[262],"CPU":[263],"2006":[264],"benchmarks,":[265],"TapeCache":[266,295],"achieves":[267],"an":[268,285,291],"average":[269,303],"improvement":[271,280,298],"7.5x,":[273],"virtually":[275],"identical":[276],"7.8x":[279],"area,":[282],"iso-capacity":[286,292],"SRAM":[287],"cache.":[288],"Compared":[289],"STT-MRAM":[293],"cache,":[294],"obtains":[296],"3.1x":[297],"area":[300],"2x":[302],"savings":[305],"along":[306],"1.1":[308],"percent":[309],"improvement.":[311]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3}],"updated_date":"2026-03-13T16:22:10.518609","created_date":"2025-10-10T00:00:00"}