{"id":"https://openalex.org/W2346173388","doi":"https://doi.org/10.1109/tc.2015.2458868","title":"Identifying the Worst Reliability Input Vectors and the Associated Critical Logic Gates","display_name":"Identifying the Worst Reliability Input Vectors and the Associated Critical Logic Gates","publication_year":2015,"publication_date":"2015-07-21","ids":{"openalex":"https://openalex.org/W2346173388","doi":"https://doi.org/10.1109/tc.2015.2458868","mag":"2346173388"},"language":"en","primary_location":{"id":"doi:10.1109/tc.2015.2458868","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2015.2458868","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027668962","display_name":"Walid Ibrahim","orcid":"https://orcid.org/0000-0003-0102-6950"},"institutions":[{"id":"https://openalex.org/I67031392","display_name":"Carleton University","ror":"https://ror.org/02qtvee93","country_code":"CA","type":"education","lineage":["https://openalex.org/I67031392"]},{"id":"https://openalex.org/I201726411","display_name":"United Arab Emirates University","ror":"https://ror.org/01km6p862","country_code":"AE","type":"education","lineage":["https://openalex.org/I201726411"]}],"countries":["AE","CA"],"is_corresponding":true,"raw_author_name":"Walid Ibrahim","raw_affiliation_strings":["Systems and Computing Engineering Department, Carleton University, Ottawa, ON, Canada","UAE University, PO Box 15551, Al Ain, UAE"],"affiliations":[{"raw_affiliation_string":"Systems and Computing Engineering Department, Carleton University, Ottawa, ON, Canada","institution_ids":["https://openalex.org/I67031392"]},{"raw_affiliation_string":"UAE University, PO Box 15551, Al Ain, UAE","institution_ids":["https://openalex.org/I201726411"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5027668962"],"corresponding_institution_ids":["https://openalex.org/I201726411","https://openalex.org/I67031392"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.17142432,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"65","issue":"6","first_page":"1748","last_page":"1760"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.7830685377120972},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.670507550239563},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5898190140724182},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5474052429199219},{"id":"https://openalex.org/keywords/circuit-reliability","display_name":"Circuit reliability","score":0.48734697699546814},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4550238251686096},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.44941434264183044},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4135870337486267},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.41045740246772766},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.36698800325393677},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14417779445648193},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09699705243110657}],"concepts":[{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.7830685377120972},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.670507550239563},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5898190140724182},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5474052429199219},{"id":"https://openalex.org/C2778309119","wikidata":"https://www.wikidata.org/wiki/Q5121614","display_name":"Circuit reliability","level":4,"score":0.48734697699546814},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4550238251686096},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.44941434264183044},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4135870337486267},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.41045740246772766},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.36698800325393677},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14417779445648193},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09699705243110657},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.2015.2458868","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2015.2458868","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W1860460518","https://openalex.org/W1968010872","https://openalex.org/W1980144252","https://openalex.org/W1994568800","https://openalex.org/W2008926433","https://openalex.org/W2010119359","https://openalex.org/W2057465926","https://openalex.org/W2063680586","https://openalex.org/W2071310017","https://openalex.org/W2083488767","https://openalex.org/W2083626899","https://openalex.org/W2084574629","https://openalex.org/W2100180510","https://openalex.org/W2100832799","https://openalex.org/W2102905107","https://openalex.org/W2104208957","https://openalex.org/W2111908353","https://openalex.org/W2112173236","https://openalex.org/W2113996606","https://openalex.org/W2125169487","https://openalex.org/W2126810113","https://openalex.org/W2127177189","https://openalex.org/W2131735165","https://openalex.org/W2131905059","https://openalex.org/W2133934114","https://openalex.org/W2138450211","https://openalex.org/W2147082520","https://openalex.org/W2159872347","https://openalex.org/W2164492816","https://openalex.org/W2165788555","https://openalex.org/W2175227516","https://openalex.org/W2497735908","https://openalex.org/W2950546180","https://openalex.org/W3144286968","https://openalex.org/W3149544844","https://openalex.org/W3182208082","https://openalex.org/W4252037114","https://openalex.org/W4299319444","https://openalex.org/W6683703935"],"related_works":["https://openalex.org/W2796521923","https://openalex.org/W1980349267","https://openalex.org/W1513105280","https://openalex.org/W95651076","https://openalex.org/W2098419840","https://openalex.org/W2140610743","https://openalex.org/W2116326546","https://openalex.org/W2770163697","https://openalex.org/W2110521006","https://openalex.org/W2151104031"],"abstract_inverted_index":{"Scaling":[0],"the":[1,6,16,31,62,68,74,77,86,96,106,128,132,140,143,146,152,158],"CMOS":[2],"devices":[3],"deep":[4],"into":[5],"nanorange":[7],"reduces":[8],"their":[9],"reliability":[10,17,39,64,75,89],"margins":[11],"significantly.":[12],"Consequently,":[13],"accurately":[14],"calculating":[15],"of":[18,41,76,105,115,127,145],"digital":[19],"nanocircuits":[20],"is":[21,47,125],"becoming":[22],"a":[23,56,92,113],"necessity":[24],"for":[25,60],"investigating":[26],"design":[27,99],"alternatives":[28],"to":[29,83,111],"optimize":[30],"trade-offs":[32],"between":[33],"area-power-delay":[34],"and":[35,43,49,67,103,124,131,142],"reliability.":[36],"However,":[37],"accurate":[38],"calculation":[40],"large":[42],"highly":[44],"connected":[45],"circuits":[46],"complex":[48],"very":[50],"time":[51],"consuming.":[52],"This":[53],"paper":[54],"proposes":[55],"progressive":[57],"consensus-based":[58],"algorithm":[59,107,118,148],"identifying":[61],"worst":[63],"input":[65],"vectors":[66],"associated":[69],"critical":[70,78],"logic":[71,133],"gates.":[72],"Improving":[73],"gates":[79],"helps":[80],"circuit":[81,87,122],"designers":[82],"effectively":[84],"improve":[85],"overall":[88],"while":[90],"having":[91],"minimal":[93],"impact":[94],"on":[95],"traditional":[97],"power-area-deal":[98],"parameters.":[100],"The":[101,117],"accuracy":[102,141],"efficiency":[104,144],"can":[108],"be":[109],"tuned":[110],"fit":[112],"variety":[114],"applications.":[116],"scales":[119],"well":[120],"with":[121],"size,":[123],"independent":[126],"interconnect":[129],"complexity":[130],"depth.":[134],"Extensive":[135],"computational":[136],"results":[137,155],"show":[138],"that":[139],"proposed":[147],"are":[149],"better":[150],"than":[151],"most":[153],"recent":[154],"reported":[156],"in":[157],"literature.":[159]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
