{"id":"https://openalex.org/W2048589567","doi":"https://doi.org/10.1109/tc.2015.2428694","title":"Bandwidth-Aware On-Line Scheduling in SMT Multicores","display_name":"Bandwidth-Aware On-Line Scheduling in SMT Multicores","publication_year":2015,"publication_date":"2015-05-01","ids":{"openalex":"https://openalex.org/W2048589567","doi":"https://doi.org/10.1109/tc.2015.2428694","mag":"2048589567"},"language":"en","primary_location":{"id":"doi:10.1109/tc.2015.2428694","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2015.2428694","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/10251/81480","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032643413","display_name":"Josu\u00e9 Feliu","orcid":"https://orcid.org/0000-0003-3017-4266"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Josue Feliu","raw_affiliation_strings":["Department of Computer Engineering (DISCA), Universitat Polit\u00e8cnica de Val\u00e8ncia, Cam\u00ed de Vera s/n, Val\u00e8ncia, Spain","[Department of Computer Engineering(DISCA), Universitat Polit\u00e8cnica de Val\u00e8ncia, Cam\u00ed de Vera s/n, Val\u00e8ncia, Spain]"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering (DISCA), Universitat Polit\u00e8cnica de Val\u00e8ncia, Cam\u00ed de Vera s/n, Val\u00e8ncia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"[Department of Computer Engineering(DISCA), Universitat Polit\u00e8cnica de Val\u00e8ncia, Cam\u00ed de Vera s/n, Val\u00e8ncia, Spain]","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044390347","display_name":"Julio Sahuquillo","orcid":"https://orcid.org/0000-0001-8630-4846"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Julio Sahuquillo","raw_affiliation_strings":["Department of Computer Engineering (DISCA), Universitat Polit\u00e8cnica de Val\u00e8ncia, Cam\u00ed de Vera s/n, Val\u00e8ncia, Spain","[Department of Computer Engineering(DISCA), Universitat Polit\u00e8cnica de Val\u00e8ncia, Cam\u00ed de Vera s/n, Val\u00e8ncia, Spain]"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering (DISCA), Universitat Polit\u00e8cnica de Val\u00e8ncia, Cam\u00ed de Vera s/n, Val\u00e8ncia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"[Department of Computer Engineering(DISCA), Universitat Polit\u00e8cnica de Val\u00e8ncia, Cam\u00ed de Vera s/n, Val\u00e8ncia, Spain]","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013237315","display_name":"Salvador Petit","orcid":"https://orcid.org/0000-0003-2426-4134"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Salvador Petit","raw_affiliation_strings":["Department of Computer Engineering (DISCA), Universitat Polit\u00e8cnica de Val\u00e8ncia, Cam\u00ed de Vera s/n, Val\u00e8ncia, Spain","[Department of Computer Engineering(DISCA), Universitat Polit\u00e8cnica de Val\u00e8ncia, Cam\u00ed de Vera s/n, Val\u00e8ncia, Spain]"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering (DISCA), Universitat Polit\u00e8cnica de Val\u00e8ncia, Cam\u00ed de Vera s/n, Val\u00e8ncia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"[Department of Computer Engineering(DISCA), Universitat Polit\u00e8cnica de Val\u00e8ncia, Cam\u00ed de Vera s/n, Val\u00e8ncia, Spain]","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040384183","display_name":"J. Duato","orcid":"https://orcid.org/0000-0002-7785-0607"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Jose Duato","raw_affiliation_strings":["Department of Computer Engineering (DISCA), Universitat Polit\u00e8cnica de Val\u00e8ncia, Cam\u00ed de Vera s/n, Val\u00e8ncia, Spain","[Department of Computer Engineering(DISCA), Universitat Polit\u00e8cnica de Val\u00e8ncia, Cam\u00ed de Vera s/n, Val\u00e8ncia, Spain]"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering (DISCA), Universitat Polit\u00e8cnica de Val\u00e8ncia, Cam\u00ed de Vera s/n, Val\u00e8ncia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"[Department of Computer Engineering(DISCA), Universitat Polit\u00e8cnica de Val\u00e8ncia, Cam\u00ed de Vera s/n, Val\u00e8ncia, Spain]","institution_ids":["https://openalex.org/I60053951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5032643413"],"corresponding_institution_ids":["https://openalex.org/I60053951"],"apc_list":null,"apc_paid":null,"fwci":1.3243,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.80616085,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"65","issue":"2","first_page":"422","last_page":"434"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.876533031463623},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.6399285793304443},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5975349545478821},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5885046720504761},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.48929139971733093},{"id":"https://openalex.org/keywords/dynamic-bandwidth-allocation","display_name":"Dynamic bandwidth allocation","score":0.4482736587524414},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.4171747863292694},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.41661885380744934},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.34821319580078125},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.32198527455329895},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2581619620323181},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.18653109669685364}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.876533031463623},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.6399285793304443},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5975349545478821},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5885046720504761},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48929139971733093},{"id":"https://openalex.org/C145062175","wikidata":"https://www.wikidata.org/wiki/Q5318947","display_name":"Dynamic bandwidth allocation","level":3,"score":0.4482736587524414},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.4171747863292694},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.41661885380744934},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.34821319580078125},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.32198527455329895},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2581619620323181},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.18653109669685364},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tc.2015.2428694","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2015.2428694","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},{"id":"pmh:oai:riunet.upv.es:10251/81480","is_oa":true,"landing_page_url":"http://hdl.handle.net/10251/81480","pdf_url":null,"source":{"id":"https://openalex.org/S4306401500","display_name":"RiuNet (Politechnical University of Valencia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I60053951","host_organization_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","host_organization_lineage":["https://openalex.org/I60053951"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:riunet.upv.es:10251/81480","is_oa":true,"landing_page_url":"http://hdl.handle.net/10251/81480","pdf_url":null,"source":{"id":"https://openalex.org/S4306401500","display_name":"RiuNet (Politechnical University of Valencia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I60053951","host_organization_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","host_organization_lineage":["https://openalex.org/I60053951"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G8213589631","display_name":null,"funder_award_id":"TIN2012-38341-C04-01","funder_id":"https://openalex.org/F4320321595","funder_display_name":"Federaci\u00f3n Espa\u00f1ola de Enfermedades Raras"}],"funders":[{"id":"https://openalex.org/F4320321595","display_name":"Federaci\u00f3n Espa\u00f1ola de Enfermedades Raras","ror":"https://ror.org/0348bpk17"},{"id":"https://openalex.org/F4320321837","display_name":"Ministerio de Econom\u00eda y Competitividad","ror":"https://ror.org/034900433"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W1581800354","https://openalex.org/W1875514780","https://openalex.org/W1971165887","https://openalex.org/W1995254820","https://openalex.org/W2007879342","https://openalex.org/W2013281054","https://openalex.org/W2017156338","https://openalex.org/W2018404774","https://openalex.org/W2031866163","https://openalex.org/W2042390223","https://openalex.org/W2052579201","https://openalex.org/W2059290792","https://openalex.org/W2096572124","https://openalex.org/W2098278566","https://openalex.org/W2100909259","https://openalex.org/W2109562980","https://openalex.org/W2120230074","https://openalex.org/W2121451934","https://openalex.org/W2129548165","https://openalex.org/W2144195166","https://openalex.org/W2146434221","https://openalex.org/W2152061572","https://openalex.org/W2165255379","https://openalex.org/W2913446311","https://openalex.org/W3112651258","https://openalex.org/W3142886131","https://openalex.org/W3144141583","https://openalex.org/W4233484638","https://openalex.org/W4238816702","https://openalex.org/W4240262711","https://openalex.org/W4250088717","https://openalex.org/W4253076565","https://openalex.org/W6652272179","https://openalex.org/W6679308475","https://openalex.org/W7034364089"],"related_works":["https://openalex.org/W2029299146","https://openalex.org/W1999486158","https://openalex.org/W2389261828","https://openalex.org/W3176276356","https://openalex.org/W2355511763","https://openalex.org/W2073876121","https://openalex.org/W2350829955","https://openalex.org/W2128382336","https://openalex.org/W2142810995","https://openalex.org/W2384579475"],"abstract_inverted_index":{"The":[0,130,150,167],"memory":[1,15,76,83,138,147],"hierarchy":[2],"plays":[3],"a":[4,51,114,172,177],"critical":[5],"role":[6],"on":[7,46,171],"the":[8,20,32,37,43,62,67,71,90,124,135,141,160,164,193],"performance":[9,68,96,184],"of":[10,106,119,137,180],"current":[11],"chip":[12],"multiprocessors.":[13],"Main":[14],"is":[16,169],"shared":[17,41],"by":[18,123,158],"all":[19],"running":[21,45],"processes,":[22],"which":[23],"can":[24,98],"cause":[25],"important":[26],"bandwidth":[27,39,77,86,125,148,156],"contention.":[28,63,149],"In":[29,49],"addition,":[30],"when":[31],"processor":[33],"implements":[34],"SMT":[35],"cores,":[36],"L1":[38,85,155,161,165],"becomes":[40],"among":[42,163],"threads":[44],"each":[47],"core.":[48],"such":[50],"case,":[52],"bandwidth-aware":[53],"schedulers":[54],"emerge":[55],"as":[56],"an":[57],"interesting":[58],"approach":[59],"to":[60,75,101,144,187,192],"mitigate":[61],"This":[64],"work":[65],"investigates":[66],"degradation":[69,97],"that":[70,81,117],"processes":[72],"suffer":[73],"due":[74],"constraints.":[78],"Experiments":[79],"show":[80],"main":[82,146],"and":[84],"contention":[87,157],"negatively":[88],"impact":[89],"process":[91,131,151],"performance;":[92],"in":[93],"both":[94],"cases,":[95],"grow":[99],"up":[100,186],"40":[102],"percent":[103,189],"for":[104],"some":[105],"applications.":[107],"To":[108],"deal":[109],"with":[110,190],"contention,":[111],"we":[112],"devise":[113],"scheduling":[115],"algorithm":[116],"consists":[118],"two":[120],"policies":[121],"guided":[122],"consumption":[126],"gathered":[127],"at":[128],"runtime.":[129],"selection":[132],"policy":[133,153],"balances":[134],"number":[136],"requests":[139],"over":[140],"execution":[142],"time":[143],"address":[145],"allocation":[152],"tackles":[154],"balancing":[159],"accesses":[162],"caches.":[166],"proposal":[168],"evaluated":[170],"Xeon":[173],"E5645":[174],"platform":[175],"using":[176],"wide":[178],"set":[179],"multiprogrammed":[181],"workloads,":[182],"achieving":[183],"benefits":[185],"6.7":[188],"respect":[191],"Linux":[194],"scheduler.":[195]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2026-03-06T13:50:29.536080","created_date":"2016-06-24T00:00:00"}