{"id":"https://openalex.org/W2032623983","doi":"https://doi.org/10.1109/tc.2003.1244946","title":"On synthesis of easily testable (k, K) circuits","display_name":"On synthesis of easily testable (k, K) circuits","publication_year":2003,"publication_date":"2003-11-01","ids":{"openalex":"https://openalex.org/W2032623983","doi":"https://doi.org/10.1109/tc.2003.1244946","mag":"2032623983"},"language":"en","primary_location":{"id":"doi:10.1109/tc.2003.1244946","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2003.1244946","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://research.tue.nl/en/publications/d4cb4937-72b1-4e51-9605-b8d0c46a4742","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006253638","display_name":"Srinath R. Naidu","orcid":"https://orcid.org/0000-0001-7512-4743"},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"S.R. Naidu","raw_affiliation_strings":["Department of Electrical Engineering, Eindhovan University of Technology, Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Eindhovan University of Technology, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I83019370"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004313289","display_name":"Vijay Chandru","orcid":"https://orcid.org/0000-0001-6175-9932"},"institutions":[{"id":"https://openalex.org/I59270414","display_name":"Indian Institute of Science Bangalore","ror":"https://ror.org/04dese585","country_code":"IN","type":"education","lineage":["https://openalex.org/I59270414"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vijay Chandru","raw_affiliation_strings":["Department of Computer Science and Automation, Indian Institute of Science, Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Automation, Indian Institute of Science, Bangalore, India","institution_ids":["https://openalex.org/I59270414"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5006253638"],"corresponding_institution_ids":["https://openalex.org/I83019370"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12839747,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"52","issue":"11","first_page":"1490","last_page":"1494"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6243330836296082},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.5367620587348938},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.529246985912323},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.4998924732208252},{"id":"https://openalex.org/keywords/boolean-circuit","display_name":"Boolean circuit","score":0.466942697763443},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.440798819065094},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.43123891949653625},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.41360923647880554},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3982238173484802},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3747708201408386},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.35086286067962646},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.342785507440567},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.324396550655365},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.11550122499465942}],"concepts":[{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6243330836296082},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.5367620587348938},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.529246985912323},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.4998924732208252},{"id":"https://openalex.org/C141796577","wikidata":"https://www.wikidata.org/wiki/Q837479","display_name":"Boolean circuit","level":3,"score":0.466942697763443},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.440798819065094},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.43123891949653625},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.41360923647880554},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3982238173484802},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3747708201408386},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.35086286067962646},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.342785507440567},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.324396550655365},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.11550122499465942},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tc.2003.1244946","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2003.1244946","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},{"id":"pmh:oai:pure.tue.nl:openaire/d4cb4937-72b1-4e51-9605-b8d0c46a4742","is_oa":true,"landing_page_url":"https://research.tue.nl/en/publications/d4cb4937-72b1-4e51-9605-b8d0c46a4742","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Naidu, S R & Chandru, V 2003, 'On Synthesis of (k,K) Circuits.', IEEE Transactions on Computers, vol. 52, no. 11, pp. 1490-1494. https://doi.org/10.1109/TC.2003.1244946","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:tue:oai:pure.tue.nl:publications/d4cb4937-72b1-4e51-9605-b8d0c46a4742","is_oa":true,"landing_page_url":"https://research.tue.nl/nl/publications/d4cb4937-72b1-4e51-9605-b8d0c46a4742","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Computers, 52(11), 1490 - 1494. IEEE Computer Society","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:pure.tue.nl:openaire/d4cb4937-72b1-4e51-9605-b8d0c46a4742","is_oa":true,"landing_page_url":"https://research.tue.nl/en/publications/d4cb4937-72b1-4e51-9605-b8d0c46a4742","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Naidu, S R & Chandru, V 2003, 'On Synthesis of (k,K) Circuits.', IEEE Transactions on Computers, vol. 52, no. 11, pp. 1490-1494. https://doi.org/10.1109/TC.2003.1244946","raw_type":"info:eu-repo/semantics/publishedVersion"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1906914439","https://openalex.org/W1985563424","https://openalex.org/W1991755800","https://openalex.org/W2000280971","https://openalex.org/W2002722727","https://openalex.org/W2011538048","https://openalex.org/W2070574955","https://openalex.org/W2085550081","https://openalex.org/W2914443076","https://openalex.org/W3021010896","https://openalex.org/W4236249712"],"related_works":["https://openalex.org/W1944601446","https://openalex.org/W87529998","https://openalex.org/W4247547172","https://openalex.org/W1750931500","https://openalex.org/W1853590888","https://openalex.org/W2397028171","https://openalex.org/W3144289157","https://openalex.org/W59126241","https://openalex.org/W2046896068","https://openalex.org/W1962044841"],"abstract_inverted_index":{"A":[0],"(k,":[1,52,94],"K)":[2,53,95],"circuit":[3],"is":[4,48],"one":[5],"which":[6],"can":[7],"be":[8,34,64],"decomposed":[9],"into":[10],"nonintersecting":[11],"blocks":[12,41],"of":[13,72,101],"gates":[14,73],"where":[15],"each":[16,32],"block":[17,33],"has":[18],"no":[19],"more":[20],"than":[21],"K":[22,85],"external":[23],"inputs,":[24],"such":[25],"that":[26,58],"the":[27,70,75,81],"graph":[28],"formed":[29],"by":[30],"letting":[31],"a":[35,45,49,90,98],"node":[36],"and":[37,77,84],"inserting":[38],"edges":[39],"between":[40],"if":[42,80],"they":[43,59],"share":[44],"signal":[46],"line,":[47],"partial":[50],"k-tree.":[51],"circuits":[54,96],"are":[55,78,86],"special":[56,99],"in":[57,66,69,74],"have":[60],"been":[61],"shown":[62],"to":[63,92],"testable":[65],"time":[67],"polynomial":[68],"number":[71],"circuit,":[76],"useful":[79],"constants":[82],"k":[83],"small.":[87],"We":[88],"demonstrate":[89],"procedure":[91],"synthesise":[93],"from":[97],"class":[100],"Boolean":[102],"expressions.":[103]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
