{"id":"https://openalex.org/W2222357280","doi":"https://doi.org/10.1109/tc.2003.1244938","title":"Modulo 2/sup n/ \u00b1 adder design using select-prefix blocks","display_name":"Modulo 2/sup n/ \u00b1 adder design using select-prefix blocks","publication_year":2003,"publication_date":"2003-11-01","ids":{"openalex":"https://openalex.org/W2222357280","doi":"https://doi.org/10.1109/tc.2003.1244938","mag":"2222357280"},"language":"en","primary_location":{"id":"doi:10.1109/tc.2003.1244938","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2003.1244938","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110093376","display_name":"C. Efstathiou","orcid":null},"institutions":[{"id":"https://openalex.org/I40479246","display_name":"Technological Educational Institute of Athens","ror":"https://ror.org/044m46d61","country_code":"GR","type":"education","lineage":["https://openalex.org/I40479246"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"C. Efstathiou","raw_affiliation_strings":["Department of Informatics, TEI Athens, Athens, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Informatics, TEI Athens, Athens, Greece","institution_ids":["https://openalex.org/I40479246"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065912730","display_name":"H.T. Vergos","orcid":null},"institutions":[{"id":"https://openalex.org/I120729142","display_name":"Research Academic Computer Technology Institute","ror":"https://ror.org/021nszj63","country_code":"GR","type":"facility","lineage":["https://openalex.org/I120729142","https://openalex.org/I4210154149"]},{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"H.T. Vergos","raw_affiliation_strings":["Computer Engineering and Informatics Department, University of Patras, Patras, Greece","Computer Technology Institute, Patras, Greece"],"affiliations":[{"raw_affiliation_string":"Computer Engineering and Informatics Department, University of Patras, Patras, Greece","institution_ids":["https://openalex.org/I174878644"]},{"raw_affiliation_string":"Computer Technology Institute, Patras, Greece","institution_ids":["https://openalex.org/I120729142"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043102404","display_name":"D. Nikolos","orcid":null},"institutions":[{"id":"https://openalex.org/I120729142","display_name":"Research Academic Computer Technology Institute","ror":"https://ror.org/021nszj63","country_code":"GR","type":"facility","lineage":["https://openalex.org/I120729142","https://openalex.org/I4210154149"]},{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"D. Nikolos","raw_affiliation_strings":["Computer Engineering and Informatics Department, University of Patras, Patras, Greece","Computer Technology Institute, Patras, Greece"],"affiliations":[{"raw_affiliation_string":"Computer Engineering and Informatics Department, University of Patras, Patras, Greece","institution_ids":["https://openalex.org/I174878644"]},{"raw_affiliation_string":"Computer Technology Institute, Patras, Greece","institution_ids":["https://openalex.org/I120729142"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5110093376"],"corresponding_institution_ids":["https://openalex.org/I40479246"],"apc_list":null,"apc_paid":null,"fwci":3.1295,"has_fulltext":false,"cited_by_count":62,"citation_normalized_percentile":{"value":0.91997737,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"52","issue":"11","first_page":"1399","last_page":"1406"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.932732343673706},{"id":"https://openalex.org/keywords/modulo","display_name":"Modulo","score":0.8424581289291382},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.6592639684677124},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6255285739898682},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5657577514648438},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5445350408554077},{"id":"https://openalex.org/keywords/modulo-operation","display_name":"Modulo operation","score":0.5007936954498291},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5002107620239258},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.4775296449661255},{"id":"https://openalex.org/keywords/prefix","display_name":"Prefix","score":0.4169953465461731},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.41494306921958923},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.38167840242385864},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.26943129301071167},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.2538469433784485},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.17883136868476868},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.12808692455291748},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.09717002511024475},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08274704217910767},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07453197240829468}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.932732343673706},{"id":"https://openalex.org/C54732982","wikidata":"https://www.wikidata.org/wiki/Q1415345","display_name":"Modulo","level":2,"score":0.8424581289291382},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.6592639684677124},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6255285739898682},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5657577514648438},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5445350408554077},{"id":"https://openalex.org/C183448482","wikidata":"https://www.wikidata.org/wiki/Q1799665","display_name":"Modulo operation","level":2,"score":0.5007936954498291},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5002107620239258},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.4775296449661255},{"id":"https://openalex.org/C141603448","wikidata":"https://www.wikidata.org/wiki/Q134830","display_name":"Prefix","level":2,"score":0.4169953465461731},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.41494306921958923},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.38167840242385864},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.26943129301071167},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.2538469433784485},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.17883136868476868},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.12808692455291748},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.09717002511024475},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08274704217910767},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07453197240829468},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.2003.1244938","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2003.1244938","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320323149","display_name":"National and Kapodistrian University of Athens","ror":"https://ror.org/04gnjpq42"},{"id":"https://openalex.org/F4320323894","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1513721953","https://openalex.org/W1523087909","https://openalex.org/W1533071485","https://openalex.org/W1587217691","https://openalex.org/W1601793793","https://openalex.org/W1605116544","https://openalex.org/W1963965124","https://openalex.org/W1971928471","https://openalex.org/W2008730004","https://openalex.org/W2034833016","https://openalex.org/W2035644239","https://openalex.org/W2056139187","https://openalex.org/W2082239458","https://openalex.org/W2097414281","https://openalex.org/W2099512056","https://openalex.org/W2099544592","https://openalex.org/W2105320410","https://openalex.org/W2118702985","https://openalex.org/W2120088694","https://openalex.org/W2122070588","https://openalex.org/W2130409149","https://openalex.org/W2143462372","https://openalex.org/W2148554131","https://openalex.org/W2149043711","https://openalex.org/W2169434178","https://openalex.org/W2312852230","https://openalex.org/W2502035975","https://openalex.org/W4250041435","https://openalex.org/W4285719527","https://openalex.org/W6724167147"],"related_works":["https://openalex.org/W2489015823","https://openalex.org/W126207292","https://openalex.org/W2516396101","https://openalex.org/W2186498568","https://openalex.org/W4295540194","https://openalex.org/W2129868416","https://openalex.org/W2364181090","https://openalex.org/W2015457513","https://openalex.org/W2122498021","https://openalex.org/W2552332380"],"abstract_inverted_index":{"We":[0,11],"present":[1],"new":[2],"design":[3],"methods":[4],"for":[5,18],"modulo":[6,20,25],"2/sup":[7,21,26],"n//spl":[8],"plusmn/1":[9],"adders.":[10],"use":[12],"the":[13,33],"same":[14],"select-prefix":[15],"addition":[16],"block":[17],"both":[19],"n/-1":[22],"and":[23,48],"diminished-one":[24],"n/+1":[27],"adder":[28],"design.":[29],"VLSI":[30],"implementations":[31],"of":[32,46],"proposed":[34],"adders":[35],"in":[36],"static":[37],"CMOS":[38],"show":[39],"that":[40],"they":[41],"achieve":[42],"an":[43],"attractive":[44],"combination":[45],"speed":[47],"area":[49],"costs.":[50]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}