{"id":"https://openalex.org/W2129202070","doi":"https://doi.org/10.1109/tc.2003.1197128","title":"Switch MSHR: a technique to reduce remote read memory access time in CC-NUMA multiprocessors","display_name":"Switch MSHR: a technique to reduce remote read memory access time in CC-NUMA multiprocessors","publication_year":2003,"publication_date":"2003-05-01","ids":{"openalex":"https://openalex.org/W2129202070","doi":"https://doi.org/10.1109/tc.2003.1197128","mag":"2129202070"},"language":"en","primary_location":{"id":"doi:10.1109/tc.2003.1197128","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2003.1197128","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048949780","display_name":"Laxmi N. Bhuyan","orcid":"https://orcid.org/0000-0002-8759-0458"},"institutions":[{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"L.N. Bhuyan","raw_affiliation_strings":["Computer Science and Engineering Department, University of California, Riverside, CA, USA","Comput. Sci. & Eng. Dept., California Univ., Riverside, CA, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science and Engineering Department, University of California, Riverside, CA, USA","institution_ids":["https://openalex.org/I103635307"]},{"raw_affiliation_string":"Comput. Sci. & Eng. Dept., California Univ., Riverside, CA, USA","institution_ids":["https://openalex.org/I103635307"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102075937","display_name":"Hujun Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hujun Wang","raw_affiliation_strings":["Department of Computer Science, Texas A and M University, College Station, TX, USA","Dept. of Comput. Sci., Texas A & M Univ., College Station, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Texas A and M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Texas A & M Univ., College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5048949780"],"corresponding_institution_ids":["https://openalex.org/I103635307"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.21187619,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"52","issue":"5","first_page":"617","last_page":"632"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8750106692314148},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.6957592964172363},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6055309772491455},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5915607810020447},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.572530210018158},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.4833504855632782},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.4800897240638733},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.4605966806411743},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.42994561791419983},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4110870957374573},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.37363967299461365},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.33421945571899414},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3254922926425934},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.2753932476043701},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.27487683296203613},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.268888920545578},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.24564480781555176},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.20948341488838196}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8750106692314148},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.6957592964172363},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6055309772491455},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5915607810020447},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.572530210018158},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.4833504855632782},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.4800897240638733},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.4605966806411743},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.42994561791419983},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4110870957374573},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.37363967299461365},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.33421945571899414},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3254922926425934},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.2753932476043701},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.27487683296203613},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.268888920545578},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.24564480781555176},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.20948341488838196},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.2003.1197128","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2003.1197128","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320313710","display_name":"Menzies School of Health Research","ror":"https://ror.org/006mbby82"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W333293752","https://openalex.org/W1555673550","https://openalex.org/W1676242600","https://openalex.org/W1876364087","https://openalex.org/W1897942055","https://openalex.org/W1970444712","https://openalex.org/W1975025054","https://openalex.org/W2009359669","https://openalex.org/W2041083729","https://openalex.org/W2096329363","https://openalex.org/W2100720297","https://openalex.org/W2110566456","https://openalex.org/W2114053923","https://openalex.org/W2124152379","https://openalex.org/W2127547524","https://openalex.org/W2144461965","https://openalex.org/W2152654963","https://openalex.org/W2153748416","https://openalex.org/W2158747750","https://openalex.org/W2163820265","https://openalex.org/W2169928889","https://openalex.org/W2171432528","https://openalex.org/W2742072063","https://openalex.org/W4230619649","https://openalex.org/W4230837033","https://openalex.org/W4237335835","https://openalex.org/W4242081832","https://openalex.org/W4254918363","https://openalex.org/W6742323129"],"related_works":["https://openalex.org/W2247651031","https://openalex.org/W254684032","https://openalex.org/W2105141138","https://openalex.org/W2090213052","https://openalex.org/W2781952239","https://openalex.org/W1495085183","https://openalex.org/W3151393245","https://openalex.org/W1848192231","https://openalex.org/W2318923906","https://openalex.org/W120214571"],"abstract_inverted_index":{"A":[0],"remote":[1,41],"memory":[2,25,42,113],"access":[3],"poses":[4],"a":[5,52,86,119,137,144,179,195],"severe":[6],"problem":[7],"for":[8,150,158],"the":[9,23,34,38,44,62,66,76,103,111,122,125,147,159,169,174,185,204],"design":[10,131,170],"of":[11,19,99,121,146,198],"CC-NUMA":[12],"multiprocessors":[13],"because":[14],"it":[15],"takes":[16],"an":[17],"order":[18],"magnitude":[20],"longer":[21],"than":[22],"local":[24],"access.":[26],"The":[27,79,105,129],"large":[28],"latency":[29],"arises":[30],"partly":[31],"due":[32],"to":[33,65,73,75,102,110,135],"increased":[35],"distance":[36],"between":[37],"processor":[39],"and":[40,115,161,183,206],"over":[43],"interconnection":[45],"network.":[46],"In":[47],"this":[48,165],"paper,":[49],"we":[50],"develop":[51],"new":[53,175],"switch":[54,95,138,176],"architecture,":[55],"called":[56],"Switch":[57],"MSHR":[58],"(SMSHR),":[59],"which":[60,140],"provides":[61,116],"cache":[63],"block":[64,114,123,149,156],"requesting":[67],"processors":[68],"without":[69],"those":[70],"requests":[71,101,109],"having":[72],"go":[74],"home":[77],"memory.":[78,104],"SMSHR":[80,106,130,160,205],"idea":[81],"is":[82,132],"based":[83],"on":[84],"providing":[85],"few":[87],"miss":[88],"status":[89],"holding":[90],"registers":[91],"(MSHRs)":[92],"in":[93,164,178],"each":[94],"that":[96,192],"keep":[97],"track":[98],"read":[100],"blocks":[107],"secondary":[108],"same":[112],"them":[117],"with":[118,194],"copy":[120,145],"when":[124],"primary":[126],"reply":[127],"returns.":[128],"then":[133],"extended":[134],"include":[136],"cache,":[139],"can":[141],"temporarily":[142],"save":[143],"data":[148,199],"later":[151],"use.":[152],"We":[153,167],"provide":[154],"basic":[155],"designs":[157],"SIVISHR+cache":[162],"architectures":[163,177],"paper.":[166],"explore":[168],"space":[171],"by":[172],"modeling":[173],"detailed":[180],"execution-driven":[181],"simulator":[182],"analyze":[184],"performance":[186],"benefits.":[187],"Our":[188],"Simulation":[189],"results":[190],"show":[191],"applications":[193],"high":[196],"degree":[197],"sharing":[200],"benefit":[201],"tremendously":[202],"from":[203],"SMSHR+cache":[207],"techniques.":[208]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}