{"id":"https://openalex.org/W2071317919","doi":"https://doi.org/10.1109/tc.2003.1183945","title":"Static and dynamic behavior of memory cell array spot defects in embedded DRAMs","display_name":"Static and dynamic behavior of memory cell array spot defects in embedded DRAMs","publication_year":2003,"publication_date":"2003-03-01","ids":{"openalex":"https://openalex.org/W2071317919","doi":"https://doi.org/10.1109/tc.2003.1183945","mag":"2071317919"},"language":"en","primary_location":{"id":"doi:10.1109/tc.2003.1183945","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2003.1183945","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021955713","display_name":"Zaid Al-Ars","orcid":"https://orcid.org/0000-0001-7670-8572"},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"Z. Al-Ars","raw_affiliation_strings":["Section of Computer Engineering, Delft University of Technnology, Delft, Netherlands","Fac. of Inf. Tech. & Syst., Delft Univ. of Technol., Netherlands"],"affiliations":[{"raw_affiliation_string":"Section of Computer Engineering, Delft University of Technnology, Delft, Netherlands","institution_ids":["https://openalex.org/I98358874"]},{"raw_affiliation_string":"Fac. of Inf. Tech. & Syst., Delft Univ. of Technol., Netherlands","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109858422","display_name":"A.J. van de Goor","orcid":null},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"A.J. van de Goor","raw_affiliation_strings":["Section of Computer Engineering, Delft University of Technnology, Delft, Netherlands","Fac. of Inf. Tech. & Syst., Delft Univ. of Technol., Netherlands"],"affiliations":[{"raw_affiliation_string":"Section of Computer Engineering, Delft University of Technnology, Delft, Netherlands","institution_ids":["https://openalex.org/I98358874"]},{"raw_affiliation_string":"Fac. of Inf. Tech. & Syst., Delft Univ. of Technol., Netherlands","institution_ids":["https://openalex.org/I98358874"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5021955713"],"corresponding_institution_ids":["https://openalex.org/I98358874"],"apc_list":null,"apc_paid":null,"fwci":0.9894,"has_fulltext":false,"cited_by_count":30,"citation_normalized_percentile":{"value":0.76336948,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"52","issue":"3","first_page":"293","last_page":"309"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8619837760925293},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.7789273262023926},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6967465877532959},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5229823589324951},{"id":"https://openalex.org/keywords/memory-cell","display_name":"Memory cell","score":0.44613343477249146},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4390980303287506},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4119035005569458},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3072549104690552},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2995148301124573},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16169744729995728},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13962066173553467},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.07931670546531677},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07145613431930542}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8619837760925293},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.7789273262023926},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6967465877532959},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5229823589324951},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.44613343477249146},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4390980303287506},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4119035005569458},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3072549104690552},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2995148301124573},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16169744729995728},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13962066173553467},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.07931670546531677},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07145613431930542},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tc.2003.1183945","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.2003.1183945","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},{"id":"pmh:oai:tudelft.nl:uuid:7049f371-19ea-4eb0-8c21-98335008f7bf","is_oa":false,"landing_page_url":"http://resolver.tudelft.nl/uuid:7049f371-19ea-4eb0-8c21-98335008f7bf","pdf_url":null,"source":{"id":"https://openalex.org/S4306400906","display_name":"Research Repository (Delft University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I98358874","host_organization_name":"Delft University of Technology","host_organization_lineage":["https://openalex.org/I98358874"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"journal article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1667843264","https://openalex.org/W1963076157","https://openalex.org/W1999581116","https://openalex.org/W2039947128","https://openalex.org/W2078063367","https://openalex.org/W2106518380","https://openalex.org/W2106935654","https://openalex.org/W2124058650","https://openalex.org/W2126771492","https://openalex.org/W2138223068","https://openalex.org/W2144828465","https://openalex.org/W2160968649","https://openalex.org/W4231901304","https://openalex.org/W4240958371","https://openalex.org/W4241517697"],"related_works":["https://openalex.org/W2127001124","https://openalex.org/W2518930778","https://openalex.org/W2534277296","https://openalex.org/W2127643145","https://openalex.org/W4313492242","https://openalex.org/W2142797216","https://openalex.org/W1639957441","https://openalex.org/W2030745981","https://openalex.org/W2134800848","https://openalex.org/W1928025959"],"abstract_inverted_index":{"Spot":[0],"defects":[1,25,44],"in":[2,9,41],"memory":[3,28,40,93],"devices":[4,67],"are":[5,45,128],"caused":[6],"by":[7,69],"imperfections":[8],"the":[10,20,27,39,43,60,75,88,104,119],"fabrication":[11],"process":[12],"of":[13,23,38,63,78,90,106],"these":[14],"devices.":[15],"In":[16,52],"order":[17],"to":[18,58,81,117],"analyze":[19,59],"faulty":[21,61,108],"effect":[22],"spot":[24],"on":[26,34],"behavior,":[29],"simulations":[30],"have":[31],"been":[32],"performed":[33],"an":[35],"electrical":[36],"model":[37],"which":[42],"injected,":[46],"causing":[47],"opens,":[48],"shorts,":[49],"or":[50],"bridges.":[51],"this":[53,83],"paper,":[54],"simulation":[55],"is":[56],"used":[57],"behavior":[62,109],"embedded":[64],"DRAM":[65],"(eDRAM)":[66],"produced":[68],"Infineon":[70],"Technologies.":[71],"The":[72,85,100],"paper":[73,101],"applies":[74],"new":[76,98],"approach":[77],"fault":[79,94,122],"primitives":[80],"perform":[82],"analysis.":[84],"analysis":[86],"shows":[87],"existence":[89],"most":[91],"traditional":[92],"models":[95],"and":[96,110],"establishes":[97,111],"ones.":[99],"also":[102,129],"investigates":[103],"concept":[105],"dynamic":[107],"its":[112],"importance":[113],"for":[114],"eDRAMs.":[115],"Conditions":[116],"test":[118],"newly":[120],"established":[121],"models,":[123],"together":[124],"with":[125],"a":[126],"test,":[127],"given.":[130]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
