{"id":"https://openalex.org/W2134426126","doi":"https://doi.org/10.1109/tc.1986.5009432","title":"Properties of Wired Logic","display_name":"Properties of Wired Logic","publication_year":1986,"publication_date":"1986-06-01","ids":{"openalex":"https://openalex.org/W2134426126","doi":"https://doi.org/10.1109/tc.1986.5009432","mag":"2134426126"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1986.5009432","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1986.5009432","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103702858","display_name":"Yahiko Kambayashi","orcid":null},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]},{"id":"https://openalex.org/I135598925","display_name":"Kyushu University","ror":"https://ror.org/00p4k0j84","country_code":"JP","type":"education","lineage":["https://openalex.org/I135598925"]}],"countries":["JP","US"],"is_corresponding":true,"raw_author_name":"Yahiko Kambayashi","raw_affiliation_strings":["Department of Computer Science and Communication Engineering, Kyushu University, Fukuoka, Japan","Department of Computer Science, University of Illinois, Urbana-Champaign, IL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Communication Engineering, Kyushu University, Fukuoka, Japan","institution_ids":["https://openalex.org/I135598925"]},{"raw_affiliation_string":"Department of Computer Science, University of Illinois, Urbana-Champaign, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036195592","display_name":"Saburo Muroga","orcid":null},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Saburo Muroga","raw_affiliation_strings":["Department of Computer Science, University of Illinois, Urbana-Champaign, IL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Illinois, Urbana-Champaign, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5103702858"],"corresponding_institution_ids":["https://openalex.org/I135598925","https://openalex.org/I157725225"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.22511507,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"C-35","issue":"6","first_page":"550","last_page":"563"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6763758659362793},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6733496189117432},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6343006491661072},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.6310313940048218},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6255743503570557},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.5797700881958008},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5765848159790039},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5185614228248596},{"id":"https://openalex.org/keywords/nand-logic","display_name":"NAND logic","score":0.516897439956665},{"id":"https://openalex.org/keywords/diode\u2013transistor-logic","display_name":"Diode\u2013transistor logic","score":0.49185895919799805},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.44953659176826477},{"id":"https://openalex.org/keywords/resistor\u2013transistor-logic","display_name":"Resistor\u2013transistor logic","score":0.41476157307624817},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3879774510860443},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.26873522996902466},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.23090773820877075},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21359524130821228},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1816120445728302},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.1273157298564911}],"concepts":[{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6763758659362793},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6733496189117432},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6343006491661072},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.6310313940048218},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6255743503570557},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.5797700881958008},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5765848159790039},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5185614228248596},{"id":"https://openalex.org/C7234692","wikidata":"https://www.wikidata.org/wiki/Q4116068","display_name":"NAND logic","level":4,"score":0.516897439956665},{"id":"https://openalex.org/C118759142","wikidata":"https://www.wikidata.org/wiki/Q173475","display_name":"Diode\u2013transistor logic","level":5,"score":0.49185895919799805},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.44953659176826477},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.41476157307624817},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3879774510860443},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.26873522996902466},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.23090773820877075},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21359524130821228},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1816120445728302},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.1273157298564911}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1986.5009432","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1986.5009432","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4699999988079071,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W837381191","https://openalex.org/W1609370892","https://openalex.org/W1627001377","https://openalex.org/W1662824729","https://openalex.org/W1813681271","https://openalex.org/W1987293891","https://openalex.org/W1990841571","https://openalex.org/W2016503438","https://openalex.org/W2028206183","https://openalex.org/W2057412438","https://openalex.org/W2057775556","https://openalex.org/W2064855093","https://openalex.org/W2081154203","https://openalex.org/W2085126740","https://openalex.org/W2121368330","https://openalex.org/W2153484041"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W1908137878","https://openalex.org/W2619968078","https://openalex.org/W2082591327","https://openalex.org/W1983370375","https://openalex.org/W2121963733","https://openalex.org/W2058822291","https://openalex.org/W2066518505","https://openalex.org/W1529529399","https://openalex.org/W1966764473"],"abstract_inverted_index":{"When":[0],"we":[1],"design":[2,95],"networks":[3,67,89,103],"with":[4,12,68,104],"NOR":[5,69,105],"or":[6],"NAND":[7],"gates":[8,70,106],"which":[9,58],"are":[10,54,59,75,81,114],"implemented":[11],"bipolar":[13],"and":[14,31,56,62,71,107],"MOS":[15],"transistors,":[16],"wired":[17,25,41,52],"logic":[18,26,42,48,53,94],"is":[19],"usually":[20],"allowed.":[21],"The":[22],"usage":[23],"of":[24,37,66,78,87],"reduces":[27],"the":[28,34,91,101],"network":[29],"cost":[30],"possibly":[32],"improves":[33],"speed":[35],"because":[36],"shorter":[38],"delays":[39],"on":[40,44],"than":[43],"a":[45],"gate.":[46],"Typical":[47],"functions":[49],"performed":[50],"by":[51,90,110],"AND":[55],"OR,":[57],"called":[60],"wired-AND":[61,72],"wired-OR,":[63],"respectively.":[64],"Properties":[65],"(or":[73],"wired-OR)":[74],"discussed.":[76],"Some":[77],"these":[79],"properties":[80],"used":[82],"in":[83],"developing":[84],"synthesis":[85,112],"procedures":[86],"optimum":[88,102],"integer":[92],"programming":[93],"method.":[96],"For":[97],"all":[98],"three-variable":[99],"functions,":[100],"wired-OR's,":[108],"designed":[109],"this":[111],"approach,":[113],"shown.":[115]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}