{"id":"https://openalex.org/W2071058948","doi":"https://doi.org/10.1109/tc.1984.5009312","title":"On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays","display_name":"On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays","publication_year":1984,"publication_date":"1984-01-01","ids":{"openalex":"https://openalex.org/W2071058948","doi":"https://doi.org/10.1109/tc.1984.5009312","mag":"2071058948"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1984.5009312","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1984.5009312","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055210733","display_name":"Israel Koren","orcid":"https://orcid.org/0000-0003-2741-7108"},"institutions":[{"id":"https://openalex.org/I174306211","display_name":"Technion \u2013 Israel Institute of Technology","ror":"https://ror.org/03qryx823","country_code":"IL","type":"education","lineage":["https://openalex.org/I174306211"]},{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["IL","US"],"is_corresponding":false,"raw_author_name":"Israel Koren","raw_affiliation_strings":["Computer Science Division, University of California at Berkeley, Berkeley, CA, USA","Department of Electrical Engineering, Technion-Israel Institute of Technology, Haifa, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science Division, University of California at Berkeley, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]},{"raw_affiliation_string":"Department of Electrical Engineering, Technion-Israel Institute of Technology, Haifa, Israel","institution_ids":["https://openalex.org/I174306211"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110173607","display_name":"Melvin A. Breuer","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]},{"id":"https://openalex.org/I4210116219","display_name":"Engineering Systems (United States)","ror":"https://ror.org/02qg60849","country_code":"US","type":"company","lineage":["https://openalex.org/I4210116219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Melvin A. Breuer","raw_affiliation_strings":["Departmlent of Electrical Engineering Systems, University of Southern California, Los Angeles, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departmlent of Electrical Engineering Systems, University of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212","https://openalex.org/I4210116219"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":13.4475,"has_fulltext":false,"cited_by_count":99,"citation_normalized_percentile":{"value":0.99270522,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"C-33","issue":"1","first_page":"21","last_page":"27"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9927999973297119,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.819085955619812},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.8146623373031616},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.7626345753669739},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6566696166992188},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5847964286804199},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5075219869613647},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.44341400265693665},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.43704739212989807},{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.43583211302757263},{"id":"https://openalex.org/keywords/processor-array","display_name":"Processor array","score":0.4117082953453064},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15523859858512878},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12548568844795227},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07345744967460632},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.07309558987617493},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.06892433762550354}],"concepts":[{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.819085955619812},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8146623373031616},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.7626345753669739},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6566696166992188},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5847964286804199},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5075219869613647},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.44341400265693665},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.43704739212989807},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.43583211302757263},{"id":"https://openalex.org/C2776189500","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Processor array","level":2,"score":0.4117082953453064},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15523859858512878},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12548568844795227},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07345744967460632},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.07309558987617493},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.06892433762550354},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1984.5009312","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1984.5009312","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1993371858","https://openalex.org/W2008521622","https://openalex.org/W2021792911","https://openalex.org/W2071058948","https://openalex.org/W2095939858","https://openalex.org/W2133009808","https://openalex.org/W2145302308"],"related_works":["https://openalex.org/W2153096481","https://openalex.org/W2148616436","https://openalex.org/W2102525122","https://openalex.org/W2158463942","https://openalex.org/W4306316843","https://openalex.org/W2036953450","https://openalex.org/W2130594209","https://openalex.org/W4245282135","https://openalex.org/W2170004886","https://openalex.org/W4300955944"],"abstract_inverted_index":{"Fault-tolerance":[0],"is":[1,21,35,101,121],"undoubtedly":[2],"a":[3,28,38,74],"desirable":[4],"property":[5],"of":[6,27,65,90,98,109,115,133],"any":[7],"processor":[8,29,33,70,93],"array.":[9,30,71],"However,":[10],"increased":[11],"design":[12],"and":[13,112,129],"implementation":[14],"costs":[15],"should":[16,58],"be":[17,59],"expected":[18],"when":[19],"fault-tolerance":[20],"being":[22],"introduced":[23],"into":[24],"the":[25,32,49,54,62,66,80,88,107,110,124,131],"architecture":[26],"When":[31],"array":[34],"implemented":[36],"within":[37],"single":[39],"VLSI":[40,92],"chip,":[41],"these":[42],"cost":[43],"increases":[44],"are":[45],"directly":[46],"related":[47],"to":[48,83,102,122],"chip":[50,76],"silicon":[51],"area.":[52],"Thus,":[53],"increase":[55],"in":[56,126],"area":[57,77,113],"weighed":[60],"against":[61],"improved":[63],"performance":[64,104],"gracefully":[67],"degrading":[68],"fault-tolerant":[69,91,117],"In":[72],"addition,":[73],"larger":[75],"might":[78],"reduce":[79],"wafer":[81,127],"yield":[82,128,134],"an":[84],"unaceptable":[85],"level":[86],"making":[87],"use":[89],"arrays":[94],"impractical.":[95],"The":[96],"objective":[97],"this":[99],"paper":[100],"devise":[103],"measures":[105],"for":[106],"evaluation":[108],"effectiveness":[111],"utilization":[114],"various":[116],"techniques.":[118],"Another":[119],"goal":[120],"analyze":[123],"reduction":[125],"investigate":[130],"possibility":[132],"enhancement":[135],"through":[136],"redundancy.":[137]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}