{"id":"https://openalex.org/W1900969659","doi":"https://doi.org/10.1109/tc.1984.1676458","title":"Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations","display_name":"Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations","publication_year":1984,"publication_date":"1984-05-01","ids":{"openalex":"https://openalex.org/W1900969659","doi":"https://doi.org/10.1109/tc.1984.1676458","mag":"1900969659"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1984.1676458","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1984.1676458","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5097797546","display_name":"Wold","orcid":null},"institutions":[{"id":"https://openalex.org/I180670191","display_name":"University of California, San Francisco","ror":"https://ror.org/043mz5j54","country_code":"US","type":"education","lineage":["https://openalex.org/I180670191"]},{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wold","raw_affiliation_strings":["Computer Sciences Division, University of California","Computer Sciences Division, University of California#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Sciences Division, University of California","institution_ids":["https://openalex.org/I180670191"]},{"raw_affiliation_string":"Computer Sciences Division, University of California#TAB#","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039393016","display_name":"Despain","orcid":null},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Despain","raw_affiliation_strings":["Computer Sciences Division, University of California, Berkeley, CA, USA","[Computer Sciences Division, University of California, Berkeley, CA, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Sciences Division, University of California, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]},{"raw_affiliation_string":"[Computer Sciences Division, University of California, Berkeley, CA, USA]","institution_ids":["https://openalex.org/I95457486"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":5.12,"has_fulltext":false,"cited_by_count":300,"citation_normalized_percentile":{"value":0.94832276,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":100},"biblio":{"volume":"C-33","issue":"5","first_page":"414","last_page":"426"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11206","display_name":"Model Reduction and Neural Networks","score":0.9937999844551086,"subfield":{"id":"https://openalex.org/subfields/3109","display_name":"Statistical and Nonlinear Physics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.8737768530845642},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.8572533130645752},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7854757308959961},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7593015432357788},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.6758682131767273},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6565915942192078},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.5007712841033936},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4707532525062561},{"id":"https://openalex.org/keywords/split-radix-fft-algorithm","display_name":"Split-radix FFT algorithm","score":0.46710410714149475},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35922300815582275},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.312811017036438},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3067089319229126},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.23464566469192505},{"id":"https://openalex.org/keywords/fourier-transform","display_name":"Fourier transform","score":0.1797555685043335},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16799262166023254},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07136821746826172},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.06232902407646179},{"id":"https://openalex.org/keywords/fourier-analysis","display_name":"Fourier analysis","score":0.062248408794403076},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.06119254231452942}],"concepts":[{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.8737768530845642},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.8572533130645752},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7854757308959961},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7593015432357788},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.6758682131767273},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6565915942192078},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.5007712841033936},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4707532525062561},{"id":"https://openalex.org/C103755468","wikidata":"https://www.wikidata.org/wiki/Q17103599","display_name":"Split-radix FFT algorithm","level":5,"score":0.46710410714149475},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35922300815582275},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.312811017036438},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3067089319229126},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.23464566469192505},{"id":"https://openalex.org/C102519508","wikidata":"https://www.wikidata.org/wiki/Q6520159","display_name":"Fourier transform","level":2,"score":0.1797555685043335},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16799262166023254},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07136821746826172},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.06232902407646179},{"id":"https://openalex.org/C203024314","wikidata":"https://www.wikidata.org/wiki/Q1365258","display_name":"Fourier analysis","level":3,"score":0.062248408794403076},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.06119254231452942},{"id":"https://openalex.org/C166386157","wikidata":"https://www.wikidata.org/wiki/Q1477735","display_name":"Short-time Fourier transform","level":4,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1984.1676458","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1984.1676458","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.4300000071525574,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1966904279","https://openalex.org/W1985765205","https://openalex.org/W1985956780","https://openalex.org/W1997654368","https://openalex.org/W1997901254","https://openalex.org/W2005015931","https://openalex.org/W2015346536","https://openalex.org/W2048332769","https://openalex.org/W2061171222","https://openalex.org/W2065387773","https://openalex.org/W2069441027","https://openalex.org/W2073086065","https://openalex.org/W2073373260","https://openalex.org/W2096207106","https://openalex.org/W2106445473","https://openalex.org/W2115452265","https://openalex.org/W2142603808","https://openalex.org/W2148192447","https://openalex.org/W2154307687","https://openalex.org/W2154410416","https://openalex.org/W2904838066","https://openalex.org/W3153574097","https://openalex.org/W4254389654","https://openalex.org/W6756928340"],"related_works":["https://openalex.org/W2185259940","https://openalex.org/W2031343199","https://openalex.org/W2113951268","https://openalex.org/W2168413811","https://openalex.org/W4226515754","https://openalex.org/W2977460836","https://openalex.org/W2144412928","https://openalex.org/W2356814585","https://openalex.org/W2948041274","https://openalex.org/W2004315237"],"abstract_inverted_index":{"In":[0],"some":[1,72],"signal":[2],"processing":[3],"applications,":[4],"it":[5,34],"is":[6],"desirable":[7],"to":[8,38,47],"build":[9,39],"very":[10],"high":[11],"performance":[12,21],"fast":[13],"Fourier":[14],"transform":[15],"(FFT)":[16],"processors.":[17],"To":[18],"meet":[19],"the":[20,30,74,78],"requirements,":[22],"these":[23,81],"processors":[24,51],"are":[25],"typically":[26],"highly":[27],"pipelined.":[28],"Until":[29],"advent":[31],"of":[32,52,65,73,80],"VLSI,":[33],"was":[35],"not":[36],"possible":[37],"a":[40,53],"single":[41],"chip":[42],"which":[43,61],"could":[44],"be":[45],"used":[46],"construct":[48],"pipeline":[49],"FFT":[50],"reasonable":[54],"size.":[55],"However,":[56],"VLSI":[57],"implementations":[58],"have":[59],"constraints":[60],"differ":[62],"from":[63],"those":[64],"discrete":[66],"implementations,":[67],"requiring":[68],"another":[69],"look":[70],"at":[71],"typical":[75],"FFT'algorithms":[76],"in":[77],"light":[79],"constraints.":[82]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":7},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":7},{"year":2018,"cited_by_count":14},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":11},{"year":2015,"cited_by_count":13},{"year":2014,"cited_by_count":24},{"year":2013,"cited_by_count":19},{"year":2012,"cited_by_count":8}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}