{"id":"https://openalex.org/W2014572095","doi":"https://doi.org/10.1109/tc.1984.1676356","title":"External Sorting in VLSI","display_name":"External Sorting in VLSI","publication_year":1984,"publication_date":"1984-10-01","ids":{"openalex":"https://openalex.org/W2014572095","doi":"https://doi.org/10.1109/tc.1984.1676356","mag":"2014572095"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1984.1676356","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1984.1676356","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068387798","display_name":"Bonuccelli","orcid":null},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Bonuccelli","raw_affiliation_strings":["Dipartimento di Informatica, Universita di Pisa, Pisa, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Informatica, Universita di Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088423208","display_name":"Lodi","orcid":null},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Lodi","raw_affiliation_strings":["Dipartimento di Informatica, Universita di Pisa, Pisa, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Informatica, Universita di Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073016367","display_name":"Linda Pagli","orcid":"https://orcid.org/0000-0003-3717-3952"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Pagli","raw_affiliation_strings":["Dipartimento di Informatica, Universita di Pisa, Pisa, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Informatica, Universita di Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5068387798"],"corresponding_institution_ids":["https://openalex.org/I108290504"],"apc_list":null,"apc_paid":null,"fwci":2.396,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.88628532,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"C-33","issue":"10","first_page":"931","last_page":"934"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9879999756813049,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9879999756813049,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9837999939918518,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9710000157356262,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.8053536415100098},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6349413394927979},{"id":"https://openalex.org/keywords/sorting","display_name":"Sorting","score":0.5581456422805786},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5127156972885132},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.37256941199302673},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2581692636013031},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1797197163105011},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.15897369384765625}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8053536415100098},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6349413394927979},{"id":"https://openalex.org/C111696304","wikidata":"https://www.wikidata.org/wiki/Q2303697","display_name":"Sorting","level":2,"score":0.5581456422805786},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5127156972885132},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.37256941199302673},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2581692636013031},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1797197163105011},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.15897369384765625}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1984.1676356","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1984.1676356","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1537957103","https://openalex.org/W1808157072","https://openalex.org/W2004592841","https://openalex.org/W2027344870","https://openalex.org/W2057982630","https://openalex.org/W2131853665","https://openalex.org/W2134845208","https://openalex.org/W2141389982","https://openalex.org/W6680874277"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W4283025278","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2082432309","https://openalex.org/W817174743","https://openalex.org/W2050492524","https://openalex.org/W4254559750","https://openalex.org/W2376932109","https://openalex.org/W2739612537"],"abstract_inverted_index":{"The":[0,22],"problem":[1,49],"of":[2,27,30],"sorting":[3,48],"n":[4],"elements":[5,16],"using":[6,50],"VLSI":[7,24],"chips":[8],"that":[9],"can":[10],"sort":[11,37],"only":[12],"q(q":[13],"<":[14],"n)":[15],"at":[17],"a":[18,28],"time":[19],"is":[20],"considered.":[21],"proposed":[23],"chip":[25],"consists":[26],"mesh":[29],"trees.":[31],"Two":[32],"classical":[33],"algorithms,":[34],"i.e.,":[35],"merge":[36],"and":[38],"bitonic":[39],"sort,":[40],"are":[41],"modified":[42],"to":[43],"efficiently":[44],"solve":[45],"the":[46],"external":[47],"this":[51],"chip.":[52]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
