{"id":"https://openalex.org/W2079285113","doi":"https://doi.org/10.1109/tc.1982.1676022","title":"MP/C: A Multiprocessor/Computer Architecture","display_name":"MP/C: A Multiprocessor/Computer Architecture","publication_year":1982,"publication_date":"1982-05-01","ids":{"openalex":"https://openalex.org/W2079285113","doi":"https://doi.org/10.1109/tc.1982.1676022","mag":"2079285113"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1982.1676022","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1982.1676022","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022243480","display_name":"Arden","orcid":null},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Arden","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, Princeton University","Department of Electrical Engineering and Computer Science, Princeton University, Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, Princeton University","institution_ids":["https://openalex.org/I20089843"]},{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001524609","display_name":"Ginosar","orcid":null},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ginosar","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, Princeton University, Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5022243480"],"corresponding_institution_ids":["https://openalex.org/I20089843"],"apc_list":null,"apc_paid":null,"fwci":10.0526,"has_fulltext":false,"cited_by_count":34,"citation_normalized_percentile":{"value":0.98019126,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"C-31","issue":"5","first_page":"455","last_page":"473"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8460744619369507},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7267810106277466},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.716413140296936},{"id":"https://openalex.org/keywords/address-space","display_name":"Address space","score":0.48883336782455444},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.45451000332832336},{"id":"https://openalex.org/keywords/nondeterministic-algorithm","display_name":"Nondeterministic algorithm","score":0.42355164885520935},{"id":"https://openalex.org/keywords/virtual-memory","display_name":"Virtual memory","score":0.42042112350463867},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3609352707862854},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2802128791809082},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.13599562644958496},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.0877726674079895}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8460744619369507},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7267810106277466},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.716413140296936},{"id":"https://openalex.org/C144240696","wikidata":"https://www.wikidata.org/wiki/Q367204","display_name":"Address space","level":2,"score":0.48883336782455444},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.45451000332832336},{"id":"https://openalex.org/C176181172","wikidata":"https://www.wikidata.org/wiki/Q3490301","display_name":"Nondeterministic algorithm","level":2,"score":0.42355164885520935},{"id":"https://openalex.org/C76399640","wikidata":"https://www.wikidata.org/wiki/Q189401","display_name":"Virtual memory","level":4,"score":0.42042112350463867},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3609352707862854},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2802128791809082},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.13599562644958496},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.0877726674079895}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1982.1676022","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1982.1676022","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":46,"referenced_works":["https://openalex.org/W85342588","https://openalex.org/W193760628","https://openalex.org/W1489433220","https://openalex.org/W1494104063","https://openalex.org/W1509443229","https://openalex.org/W1655990431","https://openalex.org/W1789713128","https://openalex.org/W1858930491","https://openalex.org/W1965635780","https://openalex.org/W1970851108","https://openalex.org/W1979136762","https://openalex.org/W1979418125","https://openalex.org/W1990242331","https://openalex.org/W1995997000","https://openalex.org/W2021022099","https://openalex.org/W2026959969","https://openalex.org/W2056928322","https://openalex.org/W2061345213","https://openalex.org/W2063388447","https://openalex.org/W2067021215","https://openalex.org/W2071118020","https://openalex.org/W2075865935","https://openalex.org/W2085013213","https://openalex.org/W2093693856","https://openalex.org/W2105986919","https://openalex.org/W2109072691","https://openalex.org/W2133998925","https://openalex.org/W2137380783","https://openalex.org/W2146788162","https://openalex.org/W2150714001","https://openalex.org/W2157999631","https://openalex.org/W2162922512","https://openalex.org/W2172184773","https://openalex.org/W2179246790","https://openalex.org/W2251484935","https://openalex.org/W2318946948","https://openalex.org/W2418656106","https://openalex.org/W2983752329","https://openalex.org/W4231492226","https://openalex.org/W4234856694","https://openalex.org/W4239997146","https://openalex.org/W4252410168","https://openalex.org/W4285719527","https://openalex.org/W6603474587","https://openalex.org/W6630562399","https://openalex.org/W6769920837"],"related_works":["https://openalex.org/W2381395788","https://openalex.org/W2078640694","https://openalex.org/W4243333834","https://openalex.org/W4243164802","https://openalex.org/W261562921","https://openalex.org/W2059093626","https://openalex.org/W2953954757","https://openalex.org/W2122250971","https://openalex.org/W2010128044","https://openalex.org/W2138847"],"abstract_inverted_index":{"A":[0,30,156],"computer":[1],"architecture":[2,174],"for":[3],"concurrent":[4,61],"computing":[5],"is":[6,34,50,63,99,111,151,159,164,175],"proposed":[7],"which":[8],"has":[9],"the":[10,21,54,74,81,87,94,104,118,172],"shared":[11],"memory":[12,78,108],"aspect":[13],"of":[14,59,76,89,96,117],"tightly":[15],"coupled":[16],"multiprocessor":[17],"systems":[18],"and":[19,73,93,103,107,121,127,134,145,161,171],"also":[20],"connection":[22],"simplicity":[23],"associated":[24],"with":[25,177],"message-connected,":[26],"loosely-coupled":[27],"multicomputer":[28],"systems.":[29],"large":[31],"address":[32,91],"space":[33],"dynamically":[35],"partitioned":[36],"into":[37],"contiguous":[38],"segments":[39],"that":[40],"can":[41],"be":[42],"accessed":[43],"by":[44,52,65],"a":[45,60,66,97,100,112,115],"single":[46],"processor.":[47,84],"The":[48,57,147],"partitioning":[49],"accomplished":[51],"switching":[53],"system":[55,158],"buses.":[56],"completion":[58],"process":[62],"signaled":[64],"processor's":[67],"return":[68],"to":[69,80,153],"an":[70,90],"idle":[71],"state":[72],"reattachment":[75,110],"its":[77,162],"segment":[79,109],"neighboring":[82],"active":[83],"In":[85],"effect,":[86],"assignment":[88],"sequence":[92],"activation":[95],"processor":[98,105],"process-fork":[101],"operation,":[102,122],"deactivation":[106],"process-join.":[113],"Following":[114],"description":[116],"MP/C":[119,149,173],"structure":[120,150],"programming":[123],"conventions":[124],"are":[125,169],"explained":[126],"demonstrated.":[128],"Applications":[129],"include":[130],"tree-structured":[131],"multiprocessing,":[132],"recursive":[133],"nondeterministic":[135],"procedures,":[136],"very":[137],"high":[138],"precision":[139],"numerical":[140],"calculations,":[141],"process-structured":[142],"operating":[143],"systems,":[144],"others.":[146],"linear":[148],"extensible":[152],"higher":[154],"dimensions.":[155],"two-dimensional":[157],"described":[160],"application":[163],"discussed.":[165],"Finally,":[166],"performance":[167],"issues":[168],"presented,":[170],"compared":[176],"related":[178],"designs.":[179]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
