{"id":"https://openalex.org/W1729943673","doi":"https://doi.org/10.1109/tc.1982.1675942","title":"Comparative Performance Analysis of Single Bus Multiprocessor Architectures","display_name":"Comparative Performance Analysis of Single Bus Multiprocessor Architectures","publication_year":1982,"publication_date":"1982-12-01","ids":{"openalex":"https://openalex.org/W1729943673","doi":"https://doi.org/10.1109/tc.1982.1675942","mag":"1729943673"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1982.1675942","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1982.1675942","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086678918","display_name":"Marsan","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Marsan","raw_affiliation_strings":["Istituto di Elettronica e Telecomunicazioni, Politecnico di Torino","Istituto di Elettronica e Telecomunicazioni, Politecnico di Turino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Istituto di Elettronica e Telecomunicazioni, Politecnico di Torino","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Istituto di Elettronica e Telecomunicazioni, Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059289837","display_name":"Balbo","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Balbo","raw_affiliation_strings":["Istituto di Elettronica e Telecomunicazioni, Politecnico di Turino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Istituto di Elettronica e Telecomunicazioni, Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038358667","display_name":"Conte","orcid":null},"institutions":[{"id":"https://openalex.org/I55143463","display_name":"University of Turin","ror":"https://ror.org/048tbm396","country_code":"IT","type":"education","lineage":["https://openalex.org/I55143463"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Conte","raw_affiliation_strings":["Istituto di Scienze dell'Informazione, Universit\u00e0 di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Istituto di Scienze dell'Informazione, Universit\u00e0 di Torino, Torino, Italy","institution_ids":["https://openalex.org/I55143463"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5086678918"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":6.9243,"has_fulltext":false,"cited_by_count":72,"citation_normalized_percentile":{"value":0.96235038,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"C-31","issue":"12","first_page":"1179","last_page":"1191"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10974","display_name":"Advanced Queuing Theory Analysis","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1404","display_name":"Management Information Systems"},"field":{"id":"https://openalex.org/fields/14","display_name":"Business, Management and Accounting"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8298537731170654},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.7918533086776733},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7083849906921387},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.4750368893146515},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4383623003959656},{"id":"https://openalex.org/keywords/markov-process","display_name":"Markov process","score":0.42726930975914},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4265727996826172},{"id":"https://openalex.org/keywords/distributed-memory","display_name":"Distributed memory","score":0.42400646209716797},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.35714659094810486},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3463553786277771},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07142642140388489}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8298537731170654},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.7918533086776733},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7083849906921387},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.4750368893146515},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4383623003959656},{"id":"https://openalex.org/C159886148","wikidata":"https://www.wikidata.org/wiki/Q176645","display_name":"Markov process","level":2,"score":0.42726930975914},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4265727996826172},{"id":"https://openalex.org/C91481028","wikidata":"https://www.wikidata.org/wiki/Q1054686","display_name":"Distributed memory","level":3,"score":0.42400646209716797},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.35714659094810486},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3463553786277771},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07142642140388489},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1982.1675942","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1982.1675942","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W114148695","https://openalex.org/W1643755943","https://openalex.org/W1937002962","https://openalex.org/W1977982296","https://openalex.org/W1991029946","https://openalex.org/W2010259083","https://openalex.org/W2014856654","https://openalex.org/W2015704557","https://openalex.org/W2040076110","https://openalex.org/W2056928322","https://openalex.org/W2067235277","https://openalex.org/W2125455820","https://openalex.org/W2154076647","https://openalex.org/W2161004322","https://openalex.org/W2323009482","https://openalex.org/W4250924839"],"related_works":["https://openalex.org/W2026512611","https://openalex.org/W1985165680","https://openalex.org/W4245497162","https://openalex.org/W2353146130","https://openalex.org/W1990817968","https://openalex.org/W2150064838","https://openalex.org/W2135766592","https://openalex.org/W2084925448","https://openalex.org/W2185094550","https://openalex.org/W2088823210"],"abstract_inverted_index":{"Markovian":[0,82],"models":[1],"are":[2,17,28,36,66],"developed":[3],"for":[4,52,68],"the":[5,44,47,58,69],"performance":[6],"analysis":[7],"and":[8,26,57],"comparison":[9],"of":[10,46,72],"several":[11],"single":[12],"bus":[13],"multiprocessor":[14],"architectures.":[15],"Processors":[16],"assumed":[18],"to":[19],"cooperate":[20],"in":[21,38,43],"a":[22,80],"message":[23],"passing":[24],"fashion,":[25],"messages":[27],"exchanged":[29],"through":[30],"common":[31,48],"memory":[32,49],"areas.":[33],"Four":[34],"architectures":[35],"considered":[37],"this":[39],"paper":[40],"which":[41],"differ":[42],"location":[45],"modules.":[50],"Contention":[51],"shared":[53],"resources":[54],"is":[55,62],"modeled":[56],"corresponding":[59],"efficiency":[60],"loss":[61],"studied.":[63],"Numerical":[64],"results":[65],"obtained":[67],"processing":[70],"power":[71],"each":[73],"architecture,":[74],"introducing":[75],"simplifying":[76],"assumptions":[77],"that":[78],"allow":[79],"compact":[81],"system":[83],"description.":[84]},"counts_by_year":[{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
