{"id":"https://openalex.org/W1991984646","doi":"https://doi.org/10.1109/tc.1982.1675880","title":"Architecture of a Programmable Digital Signal Processor","display_name":"Architecture of a Programmable Digital Signal Processor","publication_year":1982,"publication_date":"1982-01-01","ids":{"openalex":"https://openalex.org/W1991984646","doi":"https://doi.org/10.1109/tc.1982.1675880","mag":"1991984646"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1982.1675880","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1982.1675880","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5097583902","display_name":"Shively","orcid":null},"institutions":[{"id":"https://openalex.org/I72090969","display_name":"Nokia (United States)","ror":"https://ror.org/038km2573","country_code":"US","type":"company","lineage":["https://openalex.org/I2738502077","https://openalex.org/I72090969"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Shively","raw_affiliation_strings":["Bell Laboratories, Whippany, NJ, USA","BELL LABORATORIES"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bell Laboratories, Whippany, NJ, USA","institution_ids":[]},{"raw_affiliation_string":"BELL LABORATORIES","institution_ids":["https://openalex.org/I72090969"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5097583902"],"corresponding_institution_ids":["https://openalex.org/I72090969"],"apc_list":null,"apc_paid":null,"fwci":1.3881,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.81854043,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"C-31","issue":"1","first_page":"16","last_page":"22"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9455999732017517,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9455999732017517,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.9455999732017517,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9196000099182129,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7341355085372925},{"id":"https://openalex.org/keywords/digital-signal-processor","display_name":"Digital signal processor","score":0.6276597380638123},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6135592460632324},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6083236932754517},{"id":"https://openalex.org/keywords/digital-signal","display_name":"Digital signal","score":0.5722183585166931},{"id":"https://openalex.org/keywords/simple-programmable-logic-device","display_name":"Simple programmable logic device","score":0.5199519395828247},{"id":"https://openalex.org/keywords/erasable-programmable-logic-device","display_name":"Erasable programmable logic device","score":0.5173303484916687},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.515649676322937},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.49291491508483887},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.48936742544174194},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.48771771788597107},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.47986525297164917},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.4612203538417816},{"id":"https://openalex.org/keywords/macrocell-array","display_name":"Macrocell array","score":0.4586707353591919},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.4504200518131256},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.44581180810928345},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37956053018569946},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.25771600008010864},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.18676549196243286}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7341355085372925},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.6276597380638123},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6135592460632324},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6083236932754517},{"id":"https://openalex.org/C52773712","wikidata":"https://www.wikidata.org/wiki/Q175022","display_name":"Digital signal","level":3,"score":0.5722183585166931},{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.5199519395828247},{"id":"https://openalex.org/C110050671","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Erasable programmable logic device","level":5,"score":0.5173303484916687},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.515649676322937},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.49291491508483887},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.48936742544174194},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.48771771788597107},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.47986525297164917},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.4612203538417816},{"id":"https://openalex.org/C142278197","wikidata":"https://www.wikidata.org/wiki/Q4284934","display_name":"Macrocell array","level":5,"score":0.4586707353591919},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.4504200518131256},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.44581180810928345},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37956053018569946},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.25771600008010864},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.18676549196243286},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1982.1675880","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1982.1675880","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","0016-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1605331076","https://openalex.org/W2062887663","https://openalex.org/W2086913225","https://openalex.org/W2294500640","https://openalex.org/W2584271574","https://openalex.org/W4243176061","https://openalex.org/W6687709303"],"related_works":["https://openalex.org/W1528933814","https://openalex.org/W3013792460","https://openalex.org/W3117015220","https://openalex.org/W1904803855","https://openalex.org/W3022525969","https://openalex.org/W2376859467","https://openalex.org/W2466591189","https://openalex.org/W4389045693","https://openalex.org/W2054740893","https://openalex.org/W2764789987"],"abstract_inverted_index":{"The":[0],"architecture":[1],"of":[2],"a":[3],"programmable":[4],"signal":[5],"processor":[6],"designed":[7],"at":[8],"Bell":[9],"Laboratories":[10],"is":[11],"described.":[12]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
