{"id":"https://openalex.org/W2090821376","doi":"https://doi.org/10.1109/tc.1981.1675743","title":"Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits","display_name":"Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits","publication_year":1981,"publication_date":"1981-12-01","ids":{"openalex":"https://openalex.org/W2090821376","doi":"https://doi.org/10.1109/tc.1981.1675743","mag":"2090821376"},"language":"en","primary_location":{"id":"doi:10.1109/tc.1981.1675743","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1981.1675743","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064682674","display_name":"Chi-Chang Liaw","orcid":null},"institutions":[{"id":"https://openalex.org/I123946342","display_name":"Binghamton University","ror":"https://ror.org/008rmbt77","country_code":"US","type":"education","lineage":["https://openalex.org/I123946342"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Chi-Chang Liaw","raw_affiliation_strings":["Design Automation and Fault-Tolerant Computing, School of Advanced Technology, State University of New York, Binghamton, NY, USA"],"affiliations":[{"raw_affiliation_string":"Design Automation and Fault-Tolerant Computing, School of Advanced Technology, State University of New York, Binghamton, NY, USA","institution_ids":["https://openalex.org/I123946342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111422172","display_name":"Su","orcid":null},"institutions":[{"id":"https://openalex.org/I123946342","display_name":"Binghamton University","ror":"https://ror.org/008rmbt77","country_code":"US","type":"education","lineage":["https://openalex.org/I123946342"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Su","raw_affiliation_strings":["Design Automation and Fault-Tolerant Computing, School of Advanced Technology, State University of New York, Binghamton, NY, USA"],"affiliations":[{"raw_affiliation_string":"Design Automation and Fault-Tolerant Computing, School of Advanced Technology, State University of New York, Binghamton, NY, USA","institution_ids":["https://openalex.org/I123946342"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040048856","display_name":"Malaiya","orcid":null},"institutions":[{"id":"https://openalex.org/I123946342","display_name":"Binghamton University","ror":"https://ror.org/008rmbt77","country_code":"US","type":"education","lineage":["https://openalex.org/I123946342"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Malaiya","raw_affiliation_strings":["Design Automation and Fault-Tolerant Computing, School of Advanced Technology, State University of New York, Binghamton, NY, USA"],"affiliations":[{"raw_affiliation_string":"Design Automation and Fault-Tolerant Computing, School of Advanced Technology, State University of New York, Binghamton, NY, USA","institution_ids":["https://openalex.org/I123946342"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5064682674"],"corresponding_institution_ids":["https://openalex.org/I123946342"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.21866423,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"C-30","issue":"12","first_page":"989","last_page":"995"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.7341901063919067},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6739417314529419},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.624843180179596},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.45086178183555603},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.4323456287384033},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.41586390137672424},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3833402991294861},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.35473471879959106},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34166380763053894},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.28224658966064453},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16020876169204712},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13768231868743896},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.11937293410301208}],"concepts":[{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.7341901063919067},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6739417314529419},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.624843180179596},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.45086178183555603},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.4323456287384033},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.41586390137672424},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3833402991294861},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35473471879959106},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34166380763053894},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.28224658966064453},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16020876169204712},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13768231868743896},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.11937293410301208},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tc.1981.1675743","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tc.1981.1675743","pdf_url":null,"source":{"id":"https://openalex.org/S157670870","display_name":"IEEE Transactions on Computers","issn_l":"0018-9340","issn":["0018-9340","1557-9956","2326-3814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1828409155","https://openalex.org/W1958580948","https://openalex.org/W1980738663","https://openalex.org/W1981998105","https://openalex.org/W2104717686","https://openalex.org/W2117701932","https://openalex.org/W3201905549"],"related_works":["https://openalex.org/W2091833418","https://openalex.org/W2913077774","https://openalex.org/W2021253405","https://openalex.org/W4256030018","https://openalex.org/W2117873690","https://openalex.org/W3141249762","https://openalex.org/W1518694365","https://openalex.org/W2137555930","https://openalex.org/W2157154381","https://openalex.org/W2539872714"],"abstract_inverted_index":{"Practical":[0],"solutions":[1],"have":[2],"not":[3],"been":[4],"obtained":[5],"from":[6],"the":[7,11],"previous":[8],"papers":[9],"addressing":[10],"problem":[12],"of":[13],"testing":[14],"intermittent":[15,39],"faults":[16,40],"in":[17],"sequential":[18,27,51],"circuits.":[19,28,52],"Existing":[20],"methods":[21],"are":[22],"only":[23],"suitable":[24],"for":[25,38,46],"small":[26],"This":[29],"correspondence":[30],"presents":[31],"a":[32],"new":[33],"technique":[34],"to":[35],"design":[36],"test-experiments":[37],"which":[41],"can":[42],"conveniently":[43],"be":[44],"used":[45],"relatively":[47],"more":[48],"complex":[49],"synchronous":[50]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}